JPS5639649A - Check bit adding circuit - Google Patents
Check bit adding circuitInfo
- Publication number
- JPS5639649A JPS5639649A JP11480579A JP11480579A JPS5639649A JP S5639649 A JPS5639649 A JP S5639649A JP 11480579 A JP11480579 A JP 11480579A JP 11480579 A JP11480579 A JP 11480579A JP S5639649 A JPS5639649 A JP S5639649A
- Authority
- JP
- Japan
- Prior art keywords
- data
- generator
- addresses
- bit
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To equalize the output timing of a data bit to that of a check bit, by providing a memory where the same data bits as input data and a check bit are stored as address positions assigned by the input data. CONSTITUTION:Data transmission line 1 is connected to address input of code generator 3, and the data output of generator 3 to data transmission line 4. Generator 3, composed of ROM, stares the same data bits as the data, inputted via line 1a, and its parity bit at respective address positions assigned by the input data. Then when data 0000 and 0011, for example, are inputted to addresses of generator 3 from line 1a, the contents of addresses 0000 and 0011 are read. In addresses 0000 and 0011, data 0000 and 00111 with the parity bit added are stored, so that all bits of the data will be outputted from generator 3 to transmission line 4 at nearly the same timing. Thus, the need for data check timing is eliminated and the circuit design is facilitated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11480579A JPS5639649A (en) | 1979-09-06 | 1979-09-06 | Check bit adding circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11480579A JPS5639649A (en) | 1979-09-06 | 1979-09-06 | Check bit adding circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5639649A true JPS5639649A (en) | 1981-04-15 |
Family
ID=14647123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11480579A Pending JPS5639649A (en) | 1979-09-06 | 1979-09-06 | Check bit adding circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5639649A (en) |
-
1979
- 1979-09-06 JP JP11480579A patent/JPS5639649A/en active Pending
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