JPS5634231A - Logical operation circuit - Google Patents

Logical operation circuit

Info

Publication number
JPS5634231A
JPS5634231A JP11007679A JP11007679A JPS5634231A JP S5634231 A JPS5634231 A JP S5634231A JP 11007679 A JP11007679 A JP 11007679A JP 11007679 A JP11007679 A JP 11007679A JP S5634231 A JPS5634231 A JP S5634231A
Authority
JP
Japan
Prior art keywords
base
turning
trq2
constant
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11007679A
Other languages
English (en)
Inventor
Yasushi Yasuda
Hiroshi Enomoto
Katsuharu Mitono
Taketo Imaizumi
Hitoshi Omichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11007679A priority Critical patent/JPS5634231A/ja
Publication of JPS5634231A publication Critical patent/JPS5634231A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
JP11007679A 1979-08-29 1979-08-29 Logical operation circuit Pending JPS5634231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11007679A JPS5634231A (en) 1979-08-29 1979-08-29 Logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11007679A JPS5634231A (en) 1979-08-29 1979-08-29 Logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5634231A true JPS5634231A (en) 1981-04-06

Family

ID=14526419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11007679A Pending JPS5634231A (en) 1979-08-29 1979-08-29 Logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5634231A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60237718A (ja) * 1984-05-11 1985-11-26 Mitsubishi Electric Corp Ｃｒタイマ−回路
JPS61114615A (ja) * 1984-11-07 1986-06-02 エスジーエス・マイクロエレツトロニカ・エス・ピー・エー トランジスタのモノリシツク集積化スイツチング制御回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527710A (en) * 1975-07-08 1977-01-21 Yoshiro Nakamatsu Double recorder
JPS53116768A (en) * 1977-03-22 1978-10-12 Nec Corp Logical operation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527710A (en) * 1975-07-08 1977-01-21 Yoshiro Nakamatsu Double recorder
JPS53116768A (en) * 1977-03-22 1978-10-12 Nec Corp Logical operation circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60237718A (ja) * 1984-05-11 1985-11-26 Mitsubishi Electric Corp Ｃｒタイマ−回路
JPS61114615A (ja) * 1984-11-07 1986-06-02 エスジーエス・マイクロエレツトロニカ・エス・ピー・エー トランジスタのモノリシツク集積化スイツチング制御回路

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