JPS5631221A - Circuit unit including memory circuit - Google Patents
Circuit unit including memory circuitInfo
- Publication number
- JPS5631221A JPS5631221A JP10716679A JP10716679A JPS5631221A JP S5631221 A JPS5631221 A JP S5631221A JP 10716679 A JP10716679 A JP 10716679A JP 10716679 A JP10716679 A JP 10716679A JP S5631221 A JPS5631221 A JP S5631221A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- circuit
- clock signal
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
Abstract
PURPOSE:To avoid the influence of noise upon the input level to prevent malfunctions, by using the input control signal different in phase from the fundamental clock signal of the circit unit in case that the input signal is latched into the memory circuit. CONSTITUTION:In the circuit unit including memory circuit LATCH, clock input X id divided into the 1/2 frequency by flip-flop FF1, and the output is used as the fundamental clock signal in the circuit. A clock signal later than this fundamental clock signal by the 1/4 period is generated by flip-flop FF2, and signal phi*. SET is generated from this signal and the input control signal and is latched into input signal IN latch circuit LATCH. Since the input signal later than the clock signal by the 1/4 period is latched into the memory circuit fundametally in this method, the potential of the input pin is read when no noise is put on the ground level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10716679A JPS5631221A (en) | 1979-08-24 | 1979-08-24 | Circuit unit including memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10716679A JPS5631221A (en) | 1979-08-24 | 1979-08-24 | Circuit unit including memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5631221A true JPS5631221A (en) | 1981-03-30 |
Family
ID=14452151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10716679A Pending JPS5631221A (en) | 1979-08-24 | 1979-08-24 | Circuit unit including memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5631221A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5087239A (en) * | 1982-12-23 | 1992-02-11 | Tampax Limited | Tampon applicator |
-
1979
- 1979-08-24 JP JP10716679A patent/JPS5631221A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5087239A (en) * | 1982-12-23 | 1992-02-11 | Tampax Limited | Tampon applicator |
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