JPS5629701A - Sequence control device - Google Patents

Sequence control device

Info

Publication number
JPS5629701A
JPS5629701A JP10481279A JP10481279A JPS5629701A JP S5629701 A JPS5629701 A JP S5629701A JP 10481279 A JP10481279 A JP 10481279A JP 10481279 A JP10481279 A JP 10481279A JP S5629701 A JPS5629701 A JP S5629701A
Authority
JP
Japan
Prior art keywords
address
program
original program
end instruction
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10481279A
Other languages
Japanese (ja)
Inventor
Masashi Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10481279A priority Critical patent/JPS5629701A/en
Publication of JPS5629701A publication Critical patent/JPS5629701A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: To enable an alteration under operation of the sequence control, by skipping the instruction of the final address of the decoded original program and then connecting the program to be altered to the original program.
CONSTITUTION: The timing control circuit 9 switches during the 1-instruction executing timing the address designation of the memory 2 to the contents designated by the address register 8 throught the selecting circuit 11, writes the contents of data register 10 into the memory 2 and then returns the address designation to the program counter 1 immediately after the completion of the writing. In other words, the additional programs are written sequentially into the original program, and finally the END instruction is written. After this the switch 13 is turned on. Thus the first END instruction given from the initial address is skipped and then added to the original program via the final address control circuit 12. Then the additional programs are carried out to be returned to the initial address each by the END instruction of each additional program. The switch 13 is turned off after confirmation, and then the END instruction of the original program is rewritten to an inffective state. In such way, an alterlation is possible with no discontinuation of the sequence control.
COPYRIGHT: (C)1981,JPO&Japio
JP10481279A 1979-08-16 1979-08-16 Sequence control device Pending JPS5629701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10481279A JPS5629701A (en) 1979-08-16 1979-08-16 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10481279A JPS5629701A (en) 1979-08-16 1979-08-16 Sequence control device

Publications (1)

Publication Number Publication Date
JPS5629701A true JPS5629701A (en) 1981-03-25

Family

ID=14390819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10481279A Pending JPS5629701A (en) 1979-08-16 1979-08-16 Sequence control device

Country Status (1)

Country Link
JP (1) JPS5629701A (en)

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