JPS5592935A - Screen memory control system - Google Patents

Screen memory control system

Info

Publication number
JPS5592935A
JPS5592935A JP16523478A JP16523478A JPS5592935A JP S5592935 A JPS5592935 A JP S5592935A JP 16523478 A JP16523478 A JP 16523478A JP 16523478 A JP16523478 A JP 16523478A JP S5592935 A JPS5592935 A JP S5592935A
Authority
JP
Japan
Prior art keywords
code signal
command
erasing
screen memory
screen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16523478A
Other languages
Japanese (ja)
Other versions
JPS607279B2 (en
Inventor
Toshiharu Kaizawa
Shogo Takayama
Juichi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16523478A priority Critical patent/JPS607279B2/en
Publication of JPS5592935A publication Critical patent/JPS5592935A/en
Publication of JPS607279B2 publication Critical patent/JPS607279B2/en
Expired legal-status Critical Current

Links

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To rewrite the contents of a picture memory into specific codes in a short time by applying the output of a specific code signal generating circuit to a screen memory by switching and then by making use of a direct memory access circuit for write operation.
CONSTITUTION: Specific code signal generating circuit CDG generating space codes is connected to multiplexer MPX-2 and for the erasing of the entire screen, a command is given from microprocessor MPU to command register CMR to change multiplexer MPX-1 over to the direct memory access circuit DMA side while operating screen memory R/W control circuit R/WCC to the write side. At thie time, MPX-2 is switched by a command from CMR to apply the output of CDG to screen memory RAM, and space codes are written in RAM, the contents of which are changed into an all-blank code signal in a short time to complete the erasing operation. For line erasing operation, a line erasing instruction is supplied to MPU to erase a desired line.
COPYRIGHT: (C)1980,JPO&Japio
JP16523478A 1978-12-31 1978-12-31 Screen memory control method Expired JPS607279B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16523478A JPS607279B2 (en) 1978-12-31 1978-12-31 Screen memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16523478A JPS607279B2 (en) 1978-12-31 1978-12-31 Screen memory control method

Publications (2)

Publication Number Publication Date
JPS5592935A true JPS5592935A (en) 1980-07-14
JPS607279B2 JPS607279B2 (en) 1985-02-23

Family

ID=15808399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16523478A Expired JPS607279B2 (en) 1978-12-31 1978-12-31 Screen memory control method

Country Status (1)

Country Link
JP (1) JPS607279B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154891A (en) * 1982-03-10 1983-09-14 松下電器産業株式会社 Crt controller
JPS59111686A (en) * 1982-12-17 1984-06-27 オムロン株式会社 Crt color display unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154891A (en) * 1982-03-10 1983-09-14 松下電器産業株式会社 Crt controller
JPS59111686A (en) * 1982-12-17 1984-06-27 オムロン株式会社 Crt color display unit

Also Published As

Publication number Publication date
JPS607279B2 (en) 1985-02-23

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