JPS58154891A - Crt controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a small change operation of a reflex V memory in a CRT type mounting device.

A conventional CR7 display device is shown in Fig. 1. To explain it to this figure, (1) is a central processing circuit, and (to) is a C which operates according to commands (101) from the central processing circuit (1).
The RT control circuit Q) receives the write position designation signal (1011) from the central processing circuit α) and the CRT control circuit w! A selection circuit that selects either the display position signal (102) from @Kou, (4) selects [8Iw1 (position signal from the grape (
1G3), a refresh memory that outputs character/graphic information (1G4) according to Processing circuit (character/graphic information 006 that you want to display in υ)
The display position signal (104) of the RT control circuit (2) is output in accordance with the display position signal (10).

In this conventional CRT control device, the only way to rewrite the contents of the refresh memory 14) is to simply rewrite the central processing circuit (character/graphic information) one by one, which takes an hour when handling a large amount of information. .Also, when trying to retrieve data for display from refresh memo * 141, if the central processing circuit (υ is refreshed V Yume = t 14) is accessed, the display will be disrupted, so the display must be changed to 1%/%. If the central processing circuit ■ accesses the refresh memory %+(4) only during the period, that is, the synchronization period, extra time will be required, and in the end, a large amount of time will be required for rewriting. Writing the same data on the screen (e.g. erasing the screen) takes a very long time.

The present invention aims to eliminate such drawbacks of the conventional example, and includes a central processing circuit that performs calculations or input/output control, an O4 processing circuit, and a display position that is connected to the central processing circuit and indicates the display position of the CRT. A CR'I control circuit that outputs signals, a display position signal output from the CRT control circuit II, and a flexible memory that outputs character/graphic information written in advance by the central processing circuit; A command latch that latches a refresh memory rewriting command from an arithmetic processing circuit, and a buffer circuit that outputs character-graphic information to the refresh V memory according to a command from the command latch, and the command latch has a
11.The refresh command is held for one screen display period or longer, and a 111!-containing signal is supplied to the refresh command (while the command is being held), and the buffer circuit sends a character to the pre-distributed FLET V memory.・By configuring the graphic information to be output and, after completing the command-holding, to output the write-in completion (No. 6) to the central processing circuit, the same information can be generated for the reflex V memory in one screen display period. Character-graphic information OIi is now loaded, and the central processing circuit is now able to handle character and graphic information as before.
There is no need to rewrite the graphic information fc one by one.

This is a great time saver, especially when writing the same data on all screens.

An embodiment of the present invention will be described below based on the drawings. Third
In the figure, ω~(II track is the same as in Figure 1.

Central processing circuit, CRT control control circuit 1, refleximoru @ (61ij central processing circuit (Mutsu to
y y: Command latch that latches the L memory rewrite command (10 pieces), (11 is the data I output command (109) from the command latch (6) IIC! I outputs predetermined character 1 graphic information This is a buffer circuit.

The command latch ν14 is activated simultaneously with the output of the data output command (1@) to the buffer circuit (7).
) is also output as a write signal (108). After a certain period of time (one screen display period), a rewriting end signal (110) is output to the central processing circuit (2).

Figure 3 shows a set of command latches and the 7711 circuit (710μ axis diagram) in Figure 2. The leech is a buffer circuit that acts as a command latch for the rewrite command (201) from the central processing circuit α), and is a monostable ``qW chippipe v -p (ui
O command (202) outputs character-graphic information (20:l) to the reflex V memory (4) (204).

Exposure 8 is the OR circuit, and the central processing circuit (υ to O write signal (20B) and monostable mychivibrator 1)
Take the OR of the signal (202) from , Lifshitu V Yume 4
This is the *reading signal (201i) for 1141.

◆ 4 is a buffer circuit, which is a monostable mychivibrator (1
Notify the central processing circuit O) of the situation in 1) (207
) is a thing.

Next, I will explain the production of this binding book. In Figure 3,
Central processing circuit (4!It switching command from υ (20
1), a pulse is output from the monostable MVC vibrator (11) for one screen display #1. This pulse is sent to the reflex V memory (4) via an OR circuit.
It is supplied as an embedded signal (206). Also, the signal (2
02) opens the buffer circuit m- of the buffer circuit m-, and the character
4) Supply. On the other hand, the display position signal (10) from the CRT control circuit (to) shown in FIG. 2 is selected by the selection circuit 0).
The valve is arranged and supplied as a position signal (101) to the riff V-twin memory (4). Therefore, riff Vtsu V Yumemo l
14) is *”all addresses used for one display in the hIii display period and the II write signal.

The character/graphic information to be written will be supplied, and the same character/graphic information will be written to the Reflet V Yumemo 14) in one screen display period. When the tfic and J exchange is completed.

The monostable multi-V multivibrator (1-stable μ
When there is no more space, the central processing unit 111 & is notified of the end of rewriting via the buffer circuit 64 (!07).

FIGS. 4 and 5 show another embodiment of the present invention, in which the buffer circuit (71 (tiHl)) is replaced by a latch circuit (set (or (Ill) VC is replaced. In this case, monostable multivibrator (111 is write signal (10B) to refresh memory) (or (2@6)
), and the latch circuit 111 (t or 651
) for data output command (109) ('also [(20
2) ) is output, and the characters and characters from the central processing circuit 0) are output.
The latch circuit that latched the graphic information data (111) (or (20B)) (@l (9 is ll@) Karari Fretsu V Yumemory (4) and the character fist graphic information (104)
(t or (jml)) is output. Since the display position signal (102) is supplied from the CRT control circuit (2) to the selection circuit (3) to the refresh memory (4), it is different from the embodiments shown in FIGS. 2 and 3. Similarly,
The same character/graphic information is loaded into the refresh memory (4) during one screen display period.

In addition, since the latch circuit (L) (or -) is used, it becomes possible to set character/graphic information to be rewritten from the central processing circuit (α), and it becomes possible for the central processing circuit (1) to set arbitrary This means that the refresh memory can be filled with character and graphic information.

Both of the embodiments of the present invention shown in FIG. 543 and FIG. In addition, it is possible to configure the character/graphic information set in the buffer circuit (I!1) and to set the one-screen display period. In Fig. S, the buffer circuit $40 output (maximum 0?) is the central processing processor 3!1 circuit (
It goes without saying that it is also possible to generate ml inclusion at the end of writing for υ.

As described above, the writing signal and one character/graphic information are supplied to Refretsu V Yumekoi 1 during the display period, so the period is very short (1 It is possible to rewrite the ``Zufuretsu V Yume 7ri'' during the screen display period), and since a command latch is provided, the central processing circuit can perform other processing while the 4N is being changed, which is an extremely excellent effect. It is also true.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional CRT control device, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, FIG. 3 is a partial detailed diagram of FIG. 2, and FIG. 4 is a circuit diagram of another embodiment of the present invention. The circuit configuration diagram of the embodiment, FIG. 5 is a partial detailed diagram of FIG. 4. (1)・-・Central processing circuit, Q)・-CRT td
Control circuit, (4)...Riff L/"IV humor, (6
)...Command latch, (7IQ21...buffer circuit, 1altl--latch circuit, (Ill...monostable multi-vibrator, a-to-or circuit agent Yoshihiro Morimoto)

Claims (1)

[Claims] t A central processing circuit that performs calculations or input/output control, and the central processing circuit! && Connected to the ring circuit. When the display position signal of the CRT is output, a refresh function that outputs the pre-written character middle-shape information is output, and then the central processing circuit outputs the display position signal. The command latch that latches the replacement command and the command from the command latch write the letter l in the Libretsu V memory! and a buffer circuit that outputs ls information,
The command latch holds the fresh memory rewrite command for one screen display period or longer, supplies a writing signal while the command is being held to the fresh memory, and also sends a literary book graphic to the refresh memory from the buffer circuit. A CRT control device that outputs information and outputs a write end signal to the central processing circuit after command holding is completed. 2. The buffer circuit has a latch circuit, and the character-graphic information data Jl border from the central processing circuit is used as rewrite data for the fresh memory rewrite command. The CRT control device according to item 1.