JP2001184014A - Lcd control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the waiting time of a CPU1 and to prevent the flickering of the display screen of a LCD5. SOLUTION: Two pieces of SRAM6b, c are connected in parallel as memories for the display of the LCD5. The changeover of the write-in from the CPU1 to the SRAM6a, c and the read-out from the SRAM6b, c to the LCD5 is exclusively performed by opening or closing gates 7a to d and the opening and the closing of the gates 7a to d are performed by using the select signal S from a changeover control circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD control system for controlling characters and graphics displayed on an LCD using a microcomputer (hereinafter referred to as a CPU).

[0002]

2. Description of the Related Art Recently, a CPU generally uses a CPU as a control device, and an LCD display method is used to check the operation status of the controlled device and key input for changing setting conditions. Is used. The contents displayed on the LCD need to be rewritten at regular intervals.

FIG. 3 shows a schematic diagram of a conventional LCD control system capable of displaying several lines. After the data to be displayed on the LCD is written to the SRAM 6a by the CPU 1,
In response to a command from the D controller 8, the data is transferred from the SRAM 6a to the LCD 5 and displayed.

That is, after a predetermined address A of the SRAM 6a is selected and determined by the CPU 1, the data D to be displayed
It is sent to AM6a and stored. And LCD controller 8
The address of the SRAM 6a is designated, and the data stored in the SRAM 6a is transferred to the LCD 5. The LCD 5 stores the display data transferred from the SRAM 6a in synchronization with the clock pulse CP2 from the LCD controller 8. On LCD5, 1
After storing the data for the row, the data is displayed by receiving the clock pulse CP1 from the LCD controller 8. Then, the LCD 5 repeats this operation until the bottom line of the screen to display one screen, and then repeats returning to the drawing of the first line again by receiving the frame pulse FP.

In this method, the CPU 1 needs to write data to the SRAM 6a while the SRAM 6a is not outputting data to the LCD 5. However, in general, SRAM6a
Since the period during which data is output to the SRAM 6a is long, the period during which the CPU 1 can send data to the SRAM 6a is very short. Therefore, CPU1 cannot send new data to SRAM6a,
There is a problem that the waiting time becomes long.

If the CPU 1 forcibly writes data to the SRAM 6a while the SRAM 6a is outputting data to the LCD 5, the data being written to the SRAM 6a is displayed on the LCD 5 as it is. , The display screen may be disturbed. This disturbance on the display screen causes flickering, which gives the observer discomfort and anxiety.

[0007] While the CPU 1 is writing data to the SRAM 6 a, if data output from the SRAM 6 a to the LCD 5 is cut off, display of erroneous data on the LCD 5 can be prevented. However, if this operation is performed frequently, the display on the LCD 5 will not be performed smoothly, and the display screen will flicker, giving the observer discomfort and anxiety.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a CPU.
And to prevent flickering of the display screen by the LCD.

[0009]

In order to solve the above-mentioned problems, a first invention comprises a CPU, an LCD, and a memory for LCD display, and stores data displayed on the LCD by the CPU in the memory. In an LCD control method of writing and reading display data written in the memory, transferring the data to the LCD, and displaying the data, the memory is configured by connecting a plurality of SRAMs in parallel. The switching of the gate is characterized by performing exclusively using a gate, the second invention, the switching of the gate,
It is characterized in that it is performed using a Select signal from the switching control circuit.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic diagram of an LCD control using the present invention. The present invention uses a plurality of SRAMs (two SRAMs 6b and 6c are used in FIG. 1) connected in parallel. One S
While the data from CPU 1 is stored in RAM 6b, the other S
Data from the RAM 6c is read out and output to the LCD 5, and switching of data input / output to and from the SRAMs 6b and 6c is exclusively performed using the gate 7. And
The switching of the SRAMs 6b and c and the gate 7 and the like are performed using a control signal CS, and the control of the LCD 5 as described above is performed using clock pulse signals CP1 and CP2 and a frame pulse signal FP. As described above, by switching and using the two SRAMs 6b and 6c, display data from the SRAMs 6b and c to the LCD 5 can be obtained.
Interference with the write data from the CPU 1 to the SRAMs 6b and 6c can be prevented, and the display flicker on the LCD can be prevented.

[0011]

FIG. 2 shows a block diagram of an LCD control using the present invention, which will be described in detail below. The CPU 1 and the SRAM 6b are connected to the gate 7a, and the CPU 1 and the SRAM 6c are connected to the data signal via the gate 7b.
D is connected. Switching between the gates 7a and 7b is performed by a Select signal (H or L signal) from the switching control circuit 3. That is, by using the gates 7a and 7b, the CPU
1 allows data to be written to only one of the SRAM 6b and the SRAM 6c at the same time.

The address counter 2 and the SRAM 6b are connected to the gate 7
An address signal AA is connected to each of c and SRAM 6c via a gate 7d. Therefore, the address counter
The data in the SRAMs 6b and 6c can also be read individually by the address signal AA from 2. The switching of the gates 7c and 7d is performed by the switching control circuit 3. That is, at the same time, an address is sent to either the SRAM 6b or the SRAM 6c so that data can be written or read.

While data is being written to one of the SRAMs 6b and 6c, data is read from the other SRAM and stored in the LCD 5 for display. Output from the SRAMs 6b and 6c to the LCD 5 is performed via gates 7e and 7f, respectively. The switching control circuit 3 performs switching control of these gates 7e and f periodically by sensing a writing situation from the CPU 1.

In this embodiment, when the Select signal S of the switching control circuit 3 is H, the operation of permitting the passage of the signals of the gates 7b, 7c and 7e and cutting off the signals of the gates 7a, 7d and 7f is performed. I did it. And a switching control circuit
When the Select signal S of 3 is L, the gate 7a, the gate 7d,
An operation of permitting the passage of the signal through the gate 7f and cutting off the signals of the gates 7b, 7c, and 7e is performed. That is, CPU1
While writing data to one of the SRAMs 6b and 6c, data is read from the other SRAM and stored in the LCD 5.

The switching control circuit 3 sets the Select signal S to H
The operation situation in the case of is described in more detail. In this case, as described above, only the signals passing through the gates 7b, 7c, and 7e are permitted. Therefore, the data of the CPU 1 is written to the SRAM 6c. On the other hand, according to the address signal A from the address counter 2, the data in the SRAM 6b is
It is written and displayed on LCD5 through e. That is, L
The CD 5 stores the display data transferred from the SRAM 6b in synchronization with the clock pulse CP2 from the pulse generator 4. In the LCD 5, after storing data for one row, the data is displayed by the clock pulse CP1 from the pulse generator 4. Then, the LCD 5 repeats this operation until the bottom line of the screen to display one screen, and then returns to the drawing of the first line again by receiving the frame pulse FP from the pulse generation unit 4. At this time, since the gate 7f is in the signal cutoff state, even if data is written from the CPU 1 to the SRAM 6c, the content of the data is not displayed on the LCD 5. It should be noted that the path switching in the switching control circuit 3 is an H / L Select signal S, which is mutually switched.

After a lapse of a predetermined time or in response to a switching command from the CPU 1, the switching control circuit 3 inverts the Select signal S and changes the signal to an L state. In this case, only the signals passing through the gates 7a, 7d, and 7f are permitted as described above. Therefore, the data of the CPU 1 is written to the SRAM 6b. On the other hand, by the address signal A from the address counter 2, the data stored in the SRAM 6c passes through the gate 7f.
It is written to LCD5 and displayed. That is, LCD5 is SRAM
The display data transferred from 6c is stored in synchronization with the clock pulse CP2 from the pulse generator 4. In the LCD 5, after storing data for one row, the data is displayed by the clock pulse CP1 from the pulse generator 4.
LCD5 repeats this operation until the bottom line of the screen.
After displaying one screen, the process returns to the drawing of the first row again by receiving the frame pulse FP from the pulse generation unit 4. At this time, since the gate 7e is in the signal cutoff state, even if data is written from the CPU 1 to the SRAM 6b, the contents of the data are not displayed on the LCD 5.

As described above, by switching and using a plurality of SRAMs, it is possible to prevent the screen displayed on the LCD from flickering. Further, by using the present invention, the waiting time of the CPU 1 can be reduced, so that the screen displayed on the LCD 5 can be changed in a short time.

[0018]

As described above, by using the present invention, it is possible to prevent flickering of the screen displayed on the LCD and to reduce the waiting time of the CPU, so that the display can be performed in a short time. This is excellent because the screen can be changed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of the LCD control of the present invention.

FIG. 2 is a block diagram of the LCD control of the present invention.

FIG. 3 is a schematic diagram of conventional LCD control.

[Explanation of symbols]

 1: CPU 2: Address counter 3: Switching control circuit 4: Pulse generator 5: LCD 6a to c: SRAM 7: Gate, 7a to f: Gate 8: LCD controller S: Select signal CP1, CP2: Clock pulse signal FP : Frame pulse signal CS: Control signal D: Data signal A: Address signal AC: Address signal by CPU AA: Address signal by address counter

Claims (2)

[Claims] 1. A system comprising a CPU, an LCD, and a memory for LCD display,
In the LCD control method of writing data displayed on the LCD by the CPU to the memory, reading display data written to the memory, transferring the data to the LCD, and displaying the data, the memory includes a plurality of SRAMs in parallel. LC is characterized in that switching between writing and reading to and from the SRAM is performed exclusively using a gate.
D control method. 2. The switching device according to claim 1, wherein the switching of the gate is performed using a Select signal from a switching control circuit.
LCD control method described.