JPH01161454A - Memory device using dynamic type memory element - Google Patents

Abstract

PURPOSE:To realize the execution of a refreshing operation without allowing an external image processing system to be conscious of it by controlling each part so as to execute the read/write of a main storage memory chip module according to an order. CONSTITUTION:An order control means controlling each part so as to execute the read/write of the main storage memory chip modules 102-105 according to the order regardless of the difference of input/output speed between the refresh processing and the external system by regarding the state signal and the refresh demand signal of an FIFO type buffer memory 107 as input is provided. The order control circuit is constituted by a timing generating circuit 101 and a bus interface control circuit 108. Thus, the access operation can be executed without allowing the external system to be conscious of it.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory device using a dynamic memory element, and in particular to pipeline image processing in which a large amount of image data is sequentially input and sequentially processed. The present invention relates to a memory device using a dynamic memory element which is suitable as a device and which operates like a static memory element in appearance.

[Conventional technology]

Conventional pipeline image processing devices need to be able to process data continuously without disturbing the vibe line, so static memory elements that do not require refresh operations are used as main memory elements for image storage. Often used.

Memory devices using dynamic memory elements are also widely used for simple real-time image processing such as video image processing.

However, with dynamic memory devices, all different memory addresses must be accessed at least once within a certain period of time, in other words, a refresh operation is required, so only an arbitrary partial area within one image is accessed. There is a problem when using it for general purposes such as cases. Namely.

In image processing, pixel data is often read or written by sequentially accessing only a portion of the entire screen. In such cases, that area is refreshed, but This makes it difficult to control refreshes.

Note that a memory device using a dynamic memory element dedicated to images is, for example, published by Nikkei Electronics 1985.5.
-20 r pp. 195-219.

[Problem that the invention seeks to solve]

In this way, in memory devices using conventional dynamic storage elements, the repetition rate of the refresh operation depends on the operating frequency of the external system, so all addresses are accessed, as in scanning the entire screen. There was a problem that only real-time processing such as this could be executed. In addition, conventionally, refresh operations are interpolated using normal memory access, so when only a partial area of the screen is continuously read/written as described above, it is not possible to refresh the entire screen. There was also the problem.

The object of the present invention is to solve these problems and to make the refresh operation of a dynamic storage element transparent to external systems. In other words, it is an object of the present invention to provide a memory device using a dynamic memory element that can perform an access operation without making an external system aware of refresh.

[Means for solving problems]

In order to achieve the above object, a memory device using a dynamic memory element according to the present invention includes a main memory chip module for storing data, and an external system continuously reads/writes data according to a preset order. In a memory device to which writing is performed, the memory device is provided between the main memory chip module and an external system, and is in a nearly empty state where the data is less than l/N times the total capacity;
and a FIFO type buffer memory that outputs a status signal indicating that it is nearly full by 1-(1/N) times, and a main memory chip module that receives the status signal and refresh request signal as input. A feature of the present invention is that it includes a sequence control means for controlling each part so that the main memory chip module can be read/written in the correct order regardless of refresh processing and input/output speed differences with an external system.

[For production]

In the present invention, (a) the refresh operation is performed in a time-sharing manner and periodically, which is different from normal memory access, so that even if only a partial area of the screen is continuously accessed, the refresh operation can be performed normally. be able to do so. (b) In addition, there is a FIFO (First In
By providing a buffer memory of the First 0 out type, the time required for the refresh operation is made transparent to the external system, that is, the refresh operation is not made known to the external system, so that the refresh operation is not made to wait.

Furthermore, (c) a sequence control circuit (specifically, a timing generation circuit and a bus interface control circuit) is provided to change the state of the memory device according to the number of data input to the buffer memory and the time of the refresh operation. This allows data processing to be performed without depending on the operating clock of the external system or the timing or cycle of refresh operations.

Specifically, if the buffer memory becomes completely empty or, conversely, completely full, -
In order to prevent the internal operation of the device from temporarily stopping and correct refresh operation not being performed, a buffer memory with the capacity shown in the text of this example is provided, and the data input to the buffer memory is means for detecting the number of capacity based on the ratio to the total capacity. As a result,
According to the timing of the refresh operation and the data capacity of the buffer memory, the memory device can be caused to undergo state transition under the control of the sequential control circuit.

As a result, while performing the refresh operation that is essential for a dynamic memory element, it is possible to perform an external refresh operation on any partial area of the memory device for any time from any time without affecting the data processing of the external system 11. Read/write operations can be performed that are system dependent only.

〔Example〕

An embodiment of the present invention will be described below in detail with reference to the drawings. This embodiment will be described as a memory device in a pipeline data processing system that inputs and outputs data in a raster scan format.

FIG. 1A is a block diagram of a memory device showing an embodiment of the present invention.

In FIG. 1A, 102 to 105 are dynamic memory elements for storing image data, and P number (
Here, we also have 4 banks! This is a main memory chip module made up of Each image data is stored in a main memory chip module divided into pixel units. The logic circuit 106 is connected to the main memory chip module 10.
The function converts the pixel data read out in parallel from 2 to 105 into parallel to serial and writes it into the buffer memory 107 by outputting the (serial) signal 112.・This is serially parallel converted, and the signal 301 is used to send the main memory chip module 102 to ・
105 in parallel.

Buffer memory 107 converts pixel data from logic circuit 106 into signal 1 when reading out to external output bus 110.
12 and conversely, when writing raster scan data from the external input bus 111, the logic circuit 106
This is a FIFO type buffer memory for outputting pixel data to the main memory element according to No. 42 113 at the timing of the main memory element. For example, MM as the buffer memory 107.
It is sufficient to use r67413J from Company I.

Even if the transfer speed of the external buses 110 and 111 changes at an arbitrary speed below a predetermined upper limit value, data can be continuously read/written regardless of the refresh operation of the main memory chip modules 102 to 105. In order to be able to.

A sequence control circuit causes the main memory chip modules 102 to 105 to undergo state transition depending on the state of the buffer memory 107 and whether or not a refresh operation is performed.

The sequence control circuit in FIG. 1A is composed of a timing generation circuit 101 and a bus interface control circuit 108. The timing generation circuit 101 acts as a sequence control circuit and generates a timing signal for controlling the entire memory device. The bus interface control circuit 108 is
By controlling the buffer memory 107 and the external output bus 110 to output data from the buffer memory 107, and by monitoring the signal from the external input bus 111, the buffer memory 107 is controlled and the data is output to the buffer memory 107. input.

Next, four states of the main memory chip modules 102 to 105 and their state transitions will be explained.

FIG. 2 is a state transition diagram of internal states in the sequential control circuit.

The internal state of the sequential control circuit has four states (initial state, normal memory access state, refresh state, and memory A weight shape m> is provided.

In order to satisfy the access timing regulations for dynamic storage elements, state transitions are performed at memory access change points.

Each state will be explained in detail below.

201: l- In the initial state 201, the memory device is not activated by an external image processing system and no refresh operation is performed. This condition is.

By inputting the refresh start signal (when the bus clock signal = '0'), the refresh state 204 is set.
Transition to. Further, if there is no refresh activation signal and a memory access request signal is input (when the bus clock 1 signal='1'), a transition is made to the 1 normal memory access state 202.

J202: Normal memory access state 202 is a state in which the memory device is activated by an external image processing system, and image data read/write operations are executed. In this state, when the refresh start signal is input (bus clock signal =
10'), a transition is made to the refresh state 204.

Also, if the refresh start signal is not input and the memory way 1-request signal is input (bus clock 1 signal = '1', bus clock 2 signal = '0')
), the memory wait state 203 is entered.

The memory wait state 203 is a state in which the memory device is activated by an external image processing system, but normal memory access is prohibited. . In this state, no refresh operation is performed either. At this time, if the refresh activation signal is input (when the bus clock signal = '0'), the state transitions to the refresh state 204, and if the refresh activation signal is not input and the memory access request signal is input ( When the bus clock 2 signal = 11'), the state is shifted to the normal memory access state 202 (11).

The refresh state 204 is a state fB in which the memory device performs a refresh operation.

No matter what state the memory chip module is in, if the refresh activation signal is input (when the bus clock signal is 2'0'), the refresh state 7I is given priority.
! ? By transitioning to step 204 and performing a refresh operation, the contents of the memory are prevented from being destroyed. Refresh is finished.

(Refresh) When the activation signal is released, the state returns to the state before transitioning to the refresh state 204.

In the above-described sequential control circuit having four internal states, (1) In the refresh state, a signal with a repetition period determined by the refresh time required for the dynamic storage element is sent to the main memory chip modules 102 to 105 as a refresh start signal. ■When reading in normal memory access state, the buffer memory 10
Detects that buffer memory 107 is nearly full and generates a memory wait request signal; ■When writing in a normal memory access state, detects that buffer memory 107 is nearly empty and generates a request signal to memory way 1. do.

The signals necessary for controlling the sequential control circuit will be described in detail below.

FIG. 4 is a timing diagram of basic signals controlling the memory device of the present invention.

In FIG. 4, 401 is an original oscillation clock signal.

All signals that control the memory device are created based on this original oscillation clock signal.

402 is a basic clock signal that defines the input/output operation of one data between the buffer memory 107 and the logic circuit 106, and when there are P banks of the main memory chip module, only P clock signals exist. . Further, 403 is a memory clock signal having a time width of P basic clock signals 402. Within this one cycle,
PWU parallel parallel accesses are performed on the main storage memory chip module. Below, memory clock signal 40
The time for one cycle of 3 will be called a machine cycle.

404 is a bus clock signal having a time width of M cycles of memory clock I3 403. Below 7, one period of the bus clock signal 404 will be referred to as a bus cycle. In fact, normal memory access for reading/writing data is executed in R machine cycles (interval R5-1) out of M machine cycles. Further, the refresh operation is executed in one machine cycle within this bus cycle (part Z).

In FIG. 4, the refresh operation is performed at some time in the next machine cycle when the value of the bus clock signal 404 becomes 10' (here, the portion indicated by hatching).
The explanation will be given assuming that it is carried out in (Bus clock signal 4
04 value), = 'Q'.

Use as refresh start signal. In reality, the refresh operation will effectively drop the memory device's transfer rate 1-. Therefore, in order to prevent the refresh operation from being executed more than necessary, the refresh operation period is set to be twice as long as the bus cycle (K is a positive integer).

Here, K is set such that a time equivalent to -M machine cycles satisfies the minimum refresh interval time standard for memory elements.

Next, 405 in FIG. 4 is a signal indicating whether or not to execute normal memory access to the main memory chip modules 102 to 105 in the subsequent machine cycle. Hereinafter, this signal will be referred to as the bus clock 1 signal.

Next, 406 is a memory access request signal. This memory access request signal 40G will be referred to as a path clock 2 signal hereinafter.

Finally, 407 is a memory wait request signal. Thereafter, this memory wait request signal 407 is
Let's call it a signal.

In addition, in FIG. 4, M=4. R=3. = 4.

The relationship between the state transition of the sequence control circuit of the memory device (see FIG. 2) and various timing signals (see FIG. 4) will be described in detail below.

'ro 201: j 71 When the value of the bus clock signal 404 becomes JOl, a transition is made to the refresh state 204. When the value of the bus clock 1 signal 405 becomes '1', a transition is made to the normal memory access state 202.

202: 'When the value of the normal memory i access 1 & wait 1 signal 407 is '0' and the value of the pass clock 2 signal 406 is 11', the normal memory access state 202 remains.

Furthermore, when the value of the pass clock signal 404 becomes 10',
Transition to refresh state 204. weight 1 signal 4
The value of 07 becomes 11', and the bus clock 1 signal 40
When the value of 5 is 11' and the value of the bus clock 2 signal 406 is tOj, a transition is made to the memory wait state 203.

203: Memory wait state 203 when the value of the memory unit wait 1 signal 407 is 11', the value of the bus clock 1 signal 405 is 11', and the value of the path clock 2 signal 406 is J □ j Stay in. When the value of the pass clock 2 signal 406 becomes '1', the normal memory access state 202
When the value of the pass clock signal 404 becomes '0'', the state changes to the refresh state 204.

Included week 204: The value of the refresh state weight 1 signal 407 is '0', and the pass clock 2
When the value of the signal 406 becomes 11', a transition is made to the normal memory access state 202, when the value of the bus clock 1 signal 405 is '1' and the value of the path clock 2 signal 406 is 10.
', a transition is made to the memory wait state 203. When the value of the pass clock signal 404 becomes '1', the state before the transition to the refresh state 204 is restored.

How the four states described above are controlled by specific input/output operations will be explained in detail.

First, the operation of the memory device when data is supplied from the memory device to the external bus 110 will be described.

Based on the factors that cause state transitions between two states of the sequential control circuit (i.e., memory access state 202 and memory wait state 203).

Two states in the buffer memory 107 are defined: a normal state and an abnormal state. Here, the abnormal state is
When reading from the memory device, the number of data input to the buffer memory 107 is more than (1-1/N) times the total capacity, indicating a nearly full state, and when writing to the memory device, the number of data input to the buffer memory 107 is 1/N times the total capacity. The following shows the almost empty state. In addition, states other than abnormal states are defined as normal states.

The reason for considering abnormal conditions will be explained.

As described above, the state transition of the sequential control circuit is performed at a memory access change point. Therefore, even if an abnormal state is detected, the maximum memory access time is required before the input/output operation of the buffer memory 107 can actually be stopped. Therefore, even if the buffer memory 107 goes into an abnormal state, it is necessary to make it unnecessary to immediately stop input/output operations to the buffer memory 107. As a countermeasure for this, the buffer memory 107 is prevented from becoming completely empty or completely full. For this purpose, the front stage of empty state and full state is
Detected as an abnormal state.

Specifically, when the number of data input to the buffer memory 107 is almost full (abnormal state), the value of the weight 1 signal 407 becomes '1', and the state transitions from memory way 1 to state 203. do. In this state, no data is input to the buffer memory 107, so the number of data in the buffer memory 107 decreases. Therefore, after a certain arbitrary period of time has passed, the buffer memory 107 is brought out of its nearly full state and returns to its normal state. Then, the wait state is canceled at the change point of the next machine cycle.

Up to this point is the operation of the buffer memory, but in order to smoothly supply data continuously to the external bus,
It is necessary to control the memory device so that it does not become unable to send data in the memory way 1mi state 203 (the opposite abnormal state).

For this purpose, the capacity of the buffer memory 107 is set as described below.

First, the following relationship is established.

L > N-P (1) (Because the amount P that can be written to the memory chip modules 102 to 105 at one time needs to be smaller than the abnormal state L/N) Second. , in a steady state, the effective data processing speed inside the memory device needs to be higher than the data processing speed of the external image processing system, so the following relational expression is set.

(1/Tb) ・ (R/M)>1/TP... (
2) However, one cycle time of the basic clock signal 402 is T
b. 1 of the external image processing system clock signals 504;
Let the period time be TP.

Third, the time that the memory device is in the memory wait state 203 must be shorter than the time required for the memory device to enter the reverse abnormal state.

This third condition will be described below.

The following two types of cases are used to release the wait state. That is, Case 1: When the buffer memory 107 returns to the normal state, the memory wait state 203 is immediately released.

Case 2: When the buffer memory 107 returns to the normal state and the machine state returns to the state immediately before the transition to the way l- state, the memory wait state 203 is released.

In case 1, the time from transition to wait state to release is a minimum of two machine cycles because, in the worst case, a refresh operation is inserted. Therefore, as the third condition, it is necessary to satisfy the following relational expression.

(1-(1/N)-(1/N))・L-TP:>P-T
b.2 (3) In case 2, the time required to transition to and release the way I state is a minimum of M machine cycles. Therefore, as the third condition, it is necessary to satisfy the following relational expression.

(1-(1/N)-(1/N))・L-Tr>r'-T
b-M. . . . . . . . (3') The above is an explanation of the third condition.

To summarize these results, in the case 1 control method,
From equations (1), (2), and (3), the minimum value of L and the upper limit of 19 are set as follows for an image processing system having an arbitrary operating frequency.

Lll,,=Max([P・R・2・N)/(M・
(N-2) ).

P −N) ・・・・・・・・・ (4) Here, M
ax(*) means taking the larger of the two values.

Furthermore, in the case 2 control method, (1) and (2).

From equation (3'), for an image processing system having an arbitrary operating frequency, the upper limit of the minimum value L &1% of L is set as follows.

L,,=Max([P・R−N)/(N−2),
(4') Specific examples of formulas (4) and (4') are shown below.

N==8. P=4. , M=4. If R=3, case 1. In both case 2, from the second term of equations (4) and (4'), L only needs to have a minimum value of 32 words.
That is, if the minimum value is 32 words, data can be continuously read from a data processing system having an arbitrary operating frequency. If the one cycle time TP of the basic clock signal and the one cycle time TP of the external system 11 are close, M and R are each positive integers, so
From both equations (2), the value of R must also become large. Therefore, in case 2, the first term (
The left-hand equation of , ) becomes larger than the second term (the right-hand equation of , ), and accordingly, the value of 1 may also be increased.

The explanation so far is a detailed example of a sequential control circuit when outputting data from a memory device to the outside.

Next, the state transition of the order control circuit when data is supplied from the external bus 111 to the memory device, that is, in the case of a write operation, will be described in detail.

What is the abnormal state in this case? The number of data stored in the buffer memory 107 is 1 of the total capacity of the buffer memory 107.
/N times or less, which is close to empty.

At a certain arbitrary point in time, when the number of data stored in the buffer memory 107 becomes nearly empty, a transition is made to the memory wait state 203 at a change point in the machine cycle. In this state, data is not read from the buffer memory 107, so the number of data input to the buffer memory 107 increases. As a result, after a certain arbitrary period of time has elapsed, the buffer memory 107 escapes from its nearly empty state and returns to a normal state, and the wait state is released at the change point of the machine cycle. As in the case of reading, there are the following two methods for canceling the wait state.

Case 1: When the buffer memory 107 returns to the normal state, the memory wait state 203 is immediately released. in this way,
Unlike the case of reading, the memory wait state 203
Restrictive conditions are added when transitioning to , which will be described later.

Case 2: When the buffer memory 107 returns to the normal state and the machine state returns to the state immediately before the transition to memory wait state 1m 203, the wait state is released. In this method, as in the case of reading, it is necessary to store the machine state immediately before the transition to the memory wait state 203.

In both case 1 and case 2,
As in the case of reading, in order to avoid the opposite abnormal condition, that is, a state close to full, in case 1, the L
must satisfy the conditions of both equations (4), and in case 2, L must satisfy the conditions of both equations (4').

The above is an explanation of the state transition when data is supplied from the external bus to the memory device.

The above description provides a detailed description of the state transition method of the sequential control circuit for continuously inputting and outputting data to and from an external data processing system in the two cases of reading and writing.

Next, the timing generation circuit that operates the order control circuit will be described in detail.

FIG. 1B is a block diagram of the timing generation circuit in FIG. 1A, and FIGS. 1C and 1D are timings for generating control signals for the main memory chip module and logic circuit in the timing generation circuit. It is a block diagram of a circuit. In addition.

FIG. 1C and FIG. 1D will be described later.

The timing generation circuit 101, as shown in FIG. 1B,
H oscillator 120, way 1-control circuit 128, comparator 1
27, register circuit 124, 125° 126.149,
Selector 130.3 Frequency divider circuit 121.122.4 Frequency divider circuit 123. and AND circuits 129 and 131.

The basic clock signal 402 is input to the divide-by-1 circuit 121.
It is obtained by frequency-dividing the original oscillation clock signal 401 by three. Furthermore, the memory clock signal 403 is transmitted to the frequency dividing circuit 1
22, it is obtained by decoding the output bits of a P-adic counter circuit whose clock input is the basic clock signal 402. The pass clock signal 404 is obtained by decoding, in the frequency dividing circuit 123, the output bit of an M-adic counter circuit which uses the memory clock signal 402 as a lock input.

The pass clock 1 signal 405 is generated by combining the pass clock signal 404 and the activation 4 signal 424 in the AND circuit 129.
Obtained by taking ND conditions. Further, the pass clock 2 signal 406 is obtained by ANDing the bus clock 1 signal 405 and the inverted signal of the weight 1 signal 407 in the AND circuit 131.

The activation 1 signal 421 is the main memory memory chip module 1.
This is a positive logic signal for instructing readout from 02 to 105 to an external data processing system.

The activation 21′i number 422 is the flip-flop circuit 124
, the activation 1 signal 421 is used as the memory clock signal 40
It is obtained as a signal that is held at the rising edge of 3.

The activation 3 signal 423 is obtained in the flip-flop circuit 125 as a signal that holds the positive logic signal 513 indicating that the number of data input to the buffer memory 107 has become 2 or more pixels at the rising edge of the memory clock signal 403. It will be done. This signal 513 can also be directly converted by an inverted signal of the empty signal 511 from both equations (1).

The activation 4 signal 424 selects the activation 2 signal 422 when reading data from the main memory chip modules 102 to 1o5 in the selector circuit 130, and selects the activation 2 signal 422 when writing data to the main storage memory chip modules 102 to 105. In this case, the activation 3 signal 423 is obtained as a signal delayed by one machine cycle in the delay circuit 149 for timing adjustment.

The register circuit 126 is configured such that the value of the weight 1 output 407 is O.
', the pass clock signal 4°4 is sequentially stored with a delay of one machine cycle, and the value of the weight 1 signal 407 is 1.
In the case of 1', the contents of the register circuit 126 are held.

Match No. 4B 425 has a value of '1' in the comparison circuit 127 when the value of the pass clock signal 404 and the value of the register circuit 126 match, and has a value of /OI when they do not match. .

The weight 1 signal discharge 407 has a value of the activation 4 signal 424 of '1'.
', the wait control circuit 128 stores the data in the buffer memory 107 until the total capacity is (1-(1/N)).
) full signal indicating that more than 511.1/
Empty signal 512 indicating that only N or less are input. Match signal 425. This is obtained by detecting the shift 1-out data window signal 412, which is the limiting condition of case 2 in the case of writing, at the rising edge of the memory clock signal 403.

Next, FIG. 3 is a block diagram of the logic circuit in FIG. 1A.

The logic circuit 106 is connected to the main memory chip module 10
It has a function of inputting and outputting data between 2 to 105 and the buffer memory 107.

First, a read operation for supplying data to the external bus 110'' will be described.

First, the operation of the logic circuit 106 that serially inputs P pixel data 301 read out in parallel from the main memory chip modules 102 to 105 to the buffer memory 107 will be described. The data 301 of the two pixels read out in parallel is stored in the transparent latch circuit 302 at the falling edge of the latch 1 signal 413 after one machine cycle. Note that a transparent latch circuit is a circuit that is latched by the level and falling edge of a latch signal, and in addition to the latch circuit 302, the latch circuit 308 is also a transparent type. This is it.

Latch circuit 3o9. The operation is different from that of the latch circuits 501, 502, 503, etc. (7) shown in FIGS. 5A and 5B (which are latched at the rising edge of the latch signal).

After the P pixel data 301 are latched by the transparent latch circuit 302, 7 yen are loaded in parallel into the shift register circuit 303 at the rising edge of the load 1 signal 4]4. Further, a shift operation is performed in shift register circuits 303 and 304 using the basic clock signal 402 as a clock input, and after one machine cycle, all the pixels read out earlier are moved to the shift register circuit 304. Then, the first pixel is selected in the multiplexer circuit 306, and the buffer memory 10 is selected at the next rising edge of the basic clock signal 402.
7 is stored in the register circuit 309 at the previous stage.

5A and 5B are block diagrams of peripheral circuits of the buffer memory in FIG. 1A.

Data 1 stored in the register circuit 309 in FIG.
12 is written into the buffer memory 107 in one data unit according to the shift-in signal 418 shown in FIG. 5A.

In this way, in order to correctly write only valid data other than refresh data to the buffer memory 107, a data window signal is required that specifies the writable time for the data 112 stored in the register circuit 309. For this reason, the data 301 read during the refresh operation is transferred to the shift registers 303 and 30.
However, when it reaches the register circuit 309, it is necessary to set the value of the data window signal to 10' and control it so that it is not written to the buffer memory 107.

In the memory wait state 203, the shift register circuits 303 and 304 operate, and the buffer memory 10
The shift-in operation for 7 must be stopped. Therefore, shift enable 1 signal 416. The value of the second shift enable number 417 becomes 10', and the operations of the shift register circuits 303 and 304 are stopped. Furthermore, the data shift-in operation to the buffer memory 107 is also stopped.

However, in the machine cycle immediately after transition to the memory wait state 203, a normal memory cycle or refresh operation is executed. The memory data 301 read at this time is stored in the transparent latch circuit 302 at the falling edge of the latch 1 signal 413.
The data 112 stored in is input to the buffer memory 107.

When the transition to the memory wait state 203 occurs and the value of the full signal 512 becomes O' after a certain arbitrary period of time has elapsed, the buffer memory 107 returns to the normal state and the wait state is terminated at the change point of the first machine cycle. It will be canceled.

In case 1, since the read data has already been input to the transparent latch circuit 302 and the shift register circuits 303 and 304, the shift-in data window signal 411 is used as the wait 1 signal 407 (Fig. 1B, 1C).
(see figure).

In case 2 (±, unlike case 1, the shift-in data window signal 411 (see Figure 1C)
Although it is not necessary to hold the wait 1 signal 407 for only the period in which the value is 11', it is necessary to store in the register circuit 126 the machine state immediately before the transition to the wait state.

By canceling the memory wait state 203, the values of the shift 1-enable 1 signal 41G and the shift enable 2 signal 417 both become '1', and the shift 1-register circuits 303 and 304 start operating from the next rising edge of the basic clock signal 402. The data shift-in operation to the buffer memory 107 is restarted after one basic clock time.

The machine cycle immediately after the memory wait state 203 is released is not executed, but the data stored in the transparent latch circuit 302 when the memory wait state 203 was entered is shifted at the rising edge of the load 1 signal 414 one machine cycle later. 1- written to register circuit 303;

Further, it detects a signal 513 indicating that two or more pixels of data have been input to the buffer memory 107, reads out the data in accordance with a shift-out signal synchronized with a clock signal 504 of an external data processing system, and transfers the data to the transparent latch circuit 501. After storing at the falling edge of the latch 3 signal 419, it is stored in the register circuit 502 at the rising edge of the clock signal 504, and output to the external bus 110. This results in
In the case of Ek bad, the shift-in data window signal 411 is activated in the next cycle when the data of the first two pixels are input.
Even when the value of is O' and no data is input, it is possible to prevent the buffer memory 107 from becoming completely empty, allowing continuous data reading operation. It is.

Next, a write operation for receiving and taking data from the external bus 111 will be described in detail.

In FIG. 5B, data on the external bus 111 is transferred to the register circuit 500 at the rising edge of the clock (l'') at the clock signal 504.
Then, only valid data is selected and written to the buffer memory 107 in accordance with a shift-in signal synchronized with the clock signal 504. After a certain arbitrary time has elapsed, the first written data is stored in the buffer memory 107.
When the output stage reaches the output stage, the value of the output ready signal 515 indicating that data can be output asynchronously becomes 1'.

Then, at a certain appropriate timing, the value of the activation 3 signal 423 is set to 1', and the data 113 read out pixel by pixel from the buffer memory "107" according to the shift out signal 419 is read out at the falling edge of the latch 2 signal 419. The data is stored in the transparent latch circuit 308.

Next, the data 113 read out serially from the buffer memory 107 is transferred to the main memory chip modules 102 to 1.
Regarding the operation of the logic circuit 106 that writes in parallel to 05,
Explain in detail.

In the demultiplexer circuit 307 shown in FIG.
After selecting one register of
After moving the pixel data to the shift register circuit 303, the contents of the shift register circuit 303 are stored in the PW1 element parallel parallel register circuit 305 at the rising edge of the load 2 signal 415. Then, in the next machine cycle, the contents of the register circuit 305 are transferred to the main memory chip modules 102 to 102.
For 105, write in P pixel number sequence.

As in the case of reading, a data window signal is required to specify when the data 113 can be read from the buffer memory 107 to the transparent latch circuit 308. This timing needs to satisfy the following three conditions.

First of all, it is necessary to read at a timing that bypasses the refresh operation. That is, in the above operation, it is necessary to read valid data at a timing such that the next machine cycle stored in the register circuit 305 does not correspond to a refresh cycle.

Second, data for two pixels that can be accessed in parallel in one machine cycle must be read out at the same time as they are written to the main memory chip modules 102 to 105.

This is two machines that can be accessed in parallel in one machine cycle.
When the position of pixel data on the screen is fixed, a contrivance is taken to write it into the P pixel number sequence from a slightly shifted position. That is, instead of shifting the timing of reading valid data from the buffer memory 107,
By shifting the input position in the demultiplexer circuit 307, it is possible to always read data from any position at a predetermined timing.

Thirdly, when reading data from the buffer memory 107, the memory chip modules 102 to 105
The value of the operating cycle Tb of the external system is the operating cycle TP of the external system.
Because it is larger than the value of - time buffer memory 1
It is necessary to prevent 07 from becoming empty. For this reason, it is necessary to start reading after the value of the signal 513 indicating that data is input to the buffer memory 107 for two or more pixels becomes 1'.

Therefore, in the selector circuit 130 of FIG. 1B, the activation 4 signal 424 selects a signal obtained by delaying the activation 3 signal 423 by one machine cycle.

By the way, as described above, determining the timing to read data from the buffer memory 107 involves predicting future events in terms of time, and therefore it is generally impossible to implement this using a circuit.

However, since one bus cycle time is set to an integral multiple of one machine cycle time, predicting a future event is equivalent to delaying a past event, which can be realized by a circuit.

Note that, unlike the case of reading described above, in the case of writing, when the value of the shift-out data window signal 412 shown in FIG. 3 is 10', the shift register circuit 3
It is necessary to prohibit write operations and shift operations to 04.

In the memory wait state 203, the shift register circuits 303 and 304 operate, and the buffer memory 10
The shift out operation for 7 needs to be stopped.

Therefore, the values of the shift enable 1 signal 416 and the shift enable 2 signal 417 are both '0', and the value of the way 1-2 signal 408 is controlled to be 'o'.

However, since the shift-out operation is executed immediately after transitioning to the memory wait state 203, as shown in FIG. 5B, the data 113 read from the Barahuna memory 107
is stored in the transparent latch circuit 308 shown in FIG. 3 at the falling edge of the latch 2 signal 419.

When the value of the empty signal 511 becomes '0'' after a certain arbitrary time has elapsed after transitioning to the memory wait state 203, the memory wait state 203 transitions to the normal state.

Case 1. In case 2, upon release of the memory wait state 203, the shift register circuits 303 and 304 resume operation from the next rising edge of the basic clock signal 402, and data reading from the buffer memory 107 is also stopped after one basic clock time. It will be restarted.

Although the machine cycle immediately after the memory wait state M2O3 is divided by # is not executed, the data 113 stored in the transparent latch circuit 308 when the state transitioned to the memory wait state 203 is transferred to the shift register circuit 304 after one basic tarlock time. is written to one register of

Here, in case 1, memory wait state 20
It is necessary to cancel the wait state in the machine state that has the same residence as when entering the machine state 3 and under the condition that the buffer memory 107 has returned to the normal state.

However, the residence here is uniquely determined by the value of iQl, 111 of the shift-out data window signal 412 at the rising edge of the memory clock signal 403.

The reason for adding such a constraint is that if the machine states at the start and release of the memory wait state 203 have different residences, the read operation in the buffer memory 107 and the shift register circuit 303 after release of the way 1 to state 203 are , 304, discontinuity occurs in the data, so there is a risk that the same data will be shifted consecutively or data will be dropped.

The constraint is that if a machine state with the same residence is reached for the first time in one bus cycle, no state transition will occur. At a machine cycle change point in such a machine state, the value of the shift-out data window signal 412 is 10', so that the buffer memory 107 is not accessed.

Therefore, even with such a constraint, there is almost no problem that the buffer memory 107 becomes completely empty, but in the case of writing, the control method in case 1 is incomplete.

Finally, a circuit that generates read/write control signals will be described in detail.

FIGS. 1C and 1D show the configuration of a circuit that generates the control signals necessary to properly perform read/write operations.

In FIG. 1C, data access window signal 40
9 is a signal indicating that 1 normal memory access state 202 is being executed. This (ff) is used in the flip-flop circuit 132 to input the basic clock signal 402 as a clock input, and the value of the pass clock 2 signal 406 to be
In the case of 1', at the rise of the memory clock signal 403, a level signal having a value of 1 is obtained for the next one machine cycle time.

Address clock signal 410 is a signal for updating the address of the main storage memory chip module. In the flip-flop circuit 133, when the basic clock signal 402 is used as a clock input and the value of the pass clock 2 signal 406 is 111, this signal is input to the flip-flop circuit 133, and when the value of the pass clock 2 signal 406 is 111, the signal is 111 for one basic clock time at the rising edge of the memory clock signal 403.
It is obtained as a pulse signal that holds the value of . Therefore,
By normal memory access other than refresh operation,
The address is updated by accessing the main memory chip module to the P pixel number column.

The latch 1 signal 413 is used as the basic clock 913 402t & clock input in the flip-flop circuit 140 when the value of the data access window signal 409 is 1'.
In this case, it is obtained as a pulse signal that falls at the rise of the memory clock signal 403.

Latch 2 signal 419 is shift out signal 419.

The load 1 signal 414 is input to the flip-flop circuit 139 using the basic clock signal 402 as a clock input and when the weight 1 signal 407 has a value of 1 () j.
It is obtained as a pulse signal that rises at the rise of the memory clock signal 403.

The load 2 signal 415 is obtained as a pulse signal that rises at the rising edge of the memory clock signal 403 in the flip-flop circuit 140 using the basic clock signal 402 as a clock input.

The weight 2 signal 408 is obtained as a signal obtained by inputting the original oscillation clock signal 401 as a clock to the delay circuit 138 and delaying the weight 1 signal 407 by one basic tarock time.

The shift-in data window signal 411 is generated in the delay circuit 134 by using the memory clock signal 403 as a clock input and transmitting the pass clock 1 signal 405 for 3 machine cycles (from the meaning of the pass clock signal 404, a delay time of 1 machine cycle + 1 machine cycle). Shift time) Obtained as a delayed Shinsou.

In FIG. 1D, the shift-in signal 418 is generated in the delay circuit 135 by using the original oscillation clock signal 401 as the tarock input and the shift-in data window signal 41.
1 by one basic clock time, the AND circuit 153 takes the AND condition of the above signal, the inverted signal of the weight 2 signal 408, and the input ready signal 514 indicating that data can be input to the buffer memory 107, and outputs the flip-flop. In the loop circuit 155, the original oscillation clock signal 401 is used as a clock input, and the value of the above signal is 1.
1', the basic clock (1 at the falling edge of No. i 402)
A pulse having a value of 1' for the original oscillation clock time (obtained as No. 3).

The shift-out data window signal 412 causes the delay circuit 136 to delay the pass clock 1 signal 405 by (M-1) machine cycles using the memory clock signal 4o3 as a clock input, and further inputs the basic clock signal 402 as a clock input in the delay circuit 137. is obtained as a signal delayed by one basic clock time.

In FIG. 1D, the shift out signal 419 is generated in the delay circuit 138 by using the original oscillation clock signal 401 as a clock input and delaying the shift I/ara 1/data window signal 412 by one basic clock time. , the above signal is ANDed with the inverted signal of the weight 2 signal 408 and the output ready signal 515, and in the flip-flop circuit 156, the original oscillation clock signal 401 is used as the clock input, and the value of the above signal is 1.
', a pulse signal is obtained that holds the value of 1' for one original oscillation clock time at the falling edge of the basic clock signal 402.

[Effects of the Invention] As described above, according to the present invention, a large-capacity image memory device for an image processing device that performs continuous processing on arbitrary partial areas can be realized using a dynamic storage element. , and (b) by using a sequential control circuit, the ratio shown in (4) in Part 2 of the Example Book, which is related to the magnitude of the difference between the external path and the operating frequency inside the memory device, can be significantly reduced. By using a high-capacity buffer memory, refresh operations can be performed without the external image processing system being aware of it, and (Q) Read/write operations from external data processing systems are possible.

[Brief explanation of the drawing]

FIG. 1A is an overall configuration diagram of an image memory device using a dynamic storage element showing an embodiment of the present invention, FIG.
1C and 1D are block diagrams of each part of the timing signal generation circuit in FIG. 1A, respectively, including a basic timing signal generation section for the sequential control circuit,
A timing circuit for generating control signals for the main memory chip module and logic circuit, and a data input/output control signal generation circuit for the buffer memory are shown. FIG. 2 is a state transition diagram of the sequence control circuit of the memory device, and FIG. 1A is a detailed block diagram of the logic circuit, FIG. 4 is a time chart of basic timing signals of the timing generation circuit, and FIGS. 5A and 5B are block diagrams of peripheral circuits of the buffer memory in FIG. 1A. 101: Timing generation circuit, 102-105: Main memory chip module, 106: Logic circuit, 107:
Buffer memory circuit, 108: /<Sinterface control circuit, 11.0, 111: External bus, 112, 113
: data line, 120: nuclear generator, 121: 3 frequency divider circuit,
122, 123: 4 frequency divider circuit, 127: Comparator, 128
: weight control circuit, 130: selector circuit, 129,
131°141.142,143,153,154:
A.N. 0 circuit, 124-126, 132-133, 139-1
40, 155-156: Flip-flop circuit, 134
~135,137~138,149: Delay circuit, 302
．． 308: Transparent latch circuit, 303.304: Shift register circuit, 305°309=Register circuit, 306
: multiplexer circuit, 307: demultiplexer circuit, 401: counter-generated clock signal, 402: basic clock signal, 403: memory clock signal, 404: bus clock signal, 405: bus clock 1 signal, 406: bus clock 2 signal, 407: wait 1 signal, 408: way 1-2 signal, 409: data access window signal, 410 near address clock signal, 411: shift-in data window signal, 412: shift-out data window signal, 413: latch 1 signal, 414:
Road 1 signal. 415: Load 2 signal, 416: Shift enable 1 signal, 417: Shift enable 2 signal, 418: Shift in signal, 419: Shift out 1- signal, Latch 2 signal, Latch 3 signal, 421: Start 1 signal, 422: Start 2
Signal, 423: Start 3 signal, 424: Start 4 signal, 42
5-matching signal, 501: Transparent latch circuit, 502, 5
03: L/Jister circuit, 504: Clock signal, 511
: Empty signal, 512: Full signal, 513: Read start equal number, 514: Input ready signal, 5
15: Output radio signal.

Claims (1)

[Claims] 1. A memory device comprising a main memory chip module for storing data, in which data is continuously read/written in accordance with a preset order by an external system; Provided between the module and external system, data is stored at 1/1/2 of the total capacity.
A FIFO type buffer memory that outputs a status signal indicating that it is nearly empty (N times or less) and nearly full (1-(1/N) times or more), and inputs the status signal and a refresh request signal. and a sequence control means for controlling each part so that the main memory chip module can be read/written in order regardless of the refresh processing of the main memory chip module and the input/output speed difference with an external system. 1. A memory device using a dynamic memory element, characterized in that it has: 2. The above FIFO type buffer memory satisfies (L/N)>P, where the total memory capacity is L and the unit of read/write data to the main memory chip module is P (positive integer). 2. A memory device using a dynamic memory element according to claim 1, wherein a positive number N larger than 2 is set. 3. The main memory chip module stores P pieces of data in one machine cycle period (T_b・P), where one cycle time of the basic clock signal is T_b and one cycle time of the external system clock signal is T_P. In this case, valid data is read/written in R machine cycles (R<M, R, M are positive integers) out of a maximum of M machine cycles, and a refresh operation is performed. The reading/writing of the above valid data is performed in a time-sharing manner in one machine cycle every K times M machine cycles (K is a positive integer), and by performing the above operations periodically, (1/T_b)・(R/M)>(1/
2. A memory device using a dynamic storage element according to claim 1, wherein correct data is read/written to any external system having a period T_P that satisfies T_P. 4. The above-mentioned FIFO type buffer memory has a data capacity that is greater than the minimum value determined by Max [P・R・N/(N−1), P・N], so that
Claims 1 or 2, characterized in that correct data is read/written to any external system having a cycle T_P such that _b)・(R/M)>(1/T_P). A memory device using the dynamic memory element described above. 5. By using a window signal, the order control means does not write invalid data read during a refresh operation into the buffer memory during reading, and when the buffer memory is nearly full, the main memory chip The data read from the module is not written to the buffer memory, and when writing, the data during the refresh operation is not read from the buffer memory,
In addition, when the buffer memory is nearly empty, the data is controlled not to be read from the buffer memory, and the data stored in the main memory chip module and the buffer memory is 2. A memory device using a dynamic memory element according to claim 1, wherein read/write operations are performed without interfering with the operation of an external system. 6. The above-mentioned order control means performs read/write with an external system.
At the time of writing, it is detected that the number of data input to the buffer memory is P or more, and when reading data from the main memory memory chip module, it is detected that the number of data is P or more and then the number of data input to the buffer memory is Claim 1 characterized in that when the system starts reading and writes to the main memory chip module, the system also detects the same and then starts reading from the buffer memory to the main memory chip module side. A memory device using the dynamic memory element according to item 1 or 5. 7. When reading from the external system, the order control means starts reading from a point in time when the buffer memory is neither nearly empty nor nearly full, and when writing from the external system, the buffer memory By starting reading from the buffer memory to the memory chip module side at a point when the buffer memory is neither nearly empty nor nearly full, it is possible to prevent the buffer memory from temporarily becoming full at the start of operation. A memory device using a dynamic memory element according to claim 1, 5, or 6.