JP2802995B2 - Plasma display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A plasma display device that displays text information in a flowing manner operates only when display information is changed,
Write address counter means for storing the display information in the storage unit; read address counter means operable at all times independently of the write address counter means for reading the display information from the storage unit; When the above display information is changed during the operation of the address counter means,
By providing a selector that prioritizes the operation of the write address counter means, it eliminates flicker display and non-uniform brightness caused by non-uniform display time, regardless of the moving speed of data display, and eliminates non-uniform flicker. It is possible to display a high brightness. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a control circuit of a plasma display device which displays a flow character. [Prior Art] There is known a so-called scrolling plasma display device that displays a message on a horizontally long plasma display unit as it flows over time, for example. Third
FIG. 1 shows a configuration diagram of a conventional plasma display device for scroll display. The plasma display device includes an input / output timing control circuit 1, a screen memory 2, a pararail / serial (P / S) data converter 3, a shift register (SR) 4, an address counter 5, an internal clock generator 6, and a row (ROW). )
It comprises a counter 7, a decoder 8, a Y line driver 9, an X line driver 10, and a plasma display unit 11. The input / output timing control circuit 1 receives data DATA to be displayed and a write command signal from the host, and when the write command signal is at a low level, the display data DATA is written to the screen memory 2 by the address counter 5. When the write command signal is at a high level, the display data written in the screen memory 2 is read by the address counter 5, converted into serial data via the P / S data converter 3, and input to the shift register 4. You. The display data stored in the shift register 4 is shifted by a clock signal from the internal clock circuit 6 and output to the plasma display unit 11 via the X line driver 10. On the other hand, a signal from the address counter 5 is output via the row counter 7, the decoder 8, and the Y line driver 9, and displayed on the plasma display unit 11 defined by the X line driver 10 and the Y line driver 9. FIG. 4 shows a timing chart of the above operation. In FIG. 4, (a) shows the display timing of the first row, (b) shows the display timing of the second row, and (c) shows the display timing of the n-th row. In FIG. 4, a display cycle is composed of a pattern A display period and a pattern B display period, and each display period is roughly composed of an erase period Te and a write / display period _{Tw + d} . The display timing of each row also includes an erasing period te, a writing period tw, and a display period td. The timing of each line is shifted as shown in the figure due to scroll display. [Problems to be Solved by the Invention] As is clear from FIG. 4, the erasing period te and the display period td of each line of the plasma display device are different. For this reason,
There is a problem that a luminance difference occurs due to a flicker of display, a line due to a scroll speed, and a difference between display periods, and it is difficult to see. [Means for Solving the Problem] In order to solve the above problems, the present invention stores information to be displayed in a storage unit, reads out the display information from this storage unit, and flows the display information to the plasma display unit. In the plasma display device, the operation is performed only when the display information is changed, the write address counter means for storing the display information in the storage unit, and the write address counter means is independent of the write address counter means. Read address counter means for reading the display information from the storage section, and the write address counter means when the display information is changed during the operation of the read address counter means. A plasma display device having a configuration in which a selector for prioritizing an operation is provided is provided. [Operation] As address counters for accessing data in the screen memory, write address counter means and read address counter means operable independently of each other are provided, and the display of the plasma display unit is not erased. The display information read by the read address counter means is output to the plasma display unit with a predetermined timing shift so that the display information becomes a flowing character display. By not performing display erasure on the plasma display unit, the same ratio of display time is ensured for both plasma display units. More specifically, in the plasma display device of the present invention, the read address counter is always operating, and the write address counter is operated only when a write request is made. When operating the write address counter means, the selector can give priority to the write operation of the write address counter means, and the display information can be changed in a time sufficiently shorter than the display time. Thus, according to the present invention, regardless of the moving speed of the data display, the flicker display and the non-uniformity of the luminance caused by the non-uniform display time are eliminated, and the display of the uniform luminance without the flicker can be performed. Embodiment FIG. 1 shows a block diagram of a plasma display device according to an embodiment of the present invention, and FIG. 2 shows an operation timing chart of the plasma display device. 1, the same elements as those of the conventional plasma display device shown in FIG. 3 are denoted by the same reference numerals. That is, the input / output timing control circuit 1, screen memory 2, P /
S data converter 3, shift register 4, internal clock circuit 6, roll counter 7, decoder 8, Y line driver 9, X line driver 10, and plasma display unit 11.
Is equivalent to the conventional one. A write address counter 14 and a read address counter 13 are provided in place of the address counter 5 shown in FIG. The write address counter 14 displays the display data DA
When a TA is received, the display data is stored in a predetermined area of the screen memory 2. On the other hand, read address counter
Numeral 13 is for reading the display data in the screen memory 2 and displaying it on the plasma display unit 11. Write address counter
Although the read address counter 14 and the read address counter 13 operate in response to a clock signal from the internal clock circuit 6, they can operate independently. For this reason, a selector 12 is provided to adjust access to the screen memory 2 when an access request to the screen memory 2 is generated at the same time. The operation will be described below. The write address counter 14 and the read address counter 13 can operate simultaneously and independently, but the write address counter 14 operates only when there is a write request for the display data DATA from a higher order. On the other hand, the read address counter 13 is always operating.
Its operation is as shown in FIG. 2, for each row L ₁ ~L _n,
Although there are timing differences, the display time td and the rewriting time twc are defined at the same ratio. here,
Note in FIG. 2 that there is no erase time.
In the case of horizontal character display, it is desirable to erase a portion to be displayed once and then to perform a new display as in the past, but by doing so, as described above, the display time becomes longer as the line becomes later. Is shortened. Therefore, in the present embodiment, such erasure is not performed. In principle, by not performing display erasure, the possibility of lack of clarity in switching the cross flow may occur.However, the rewriting time t wc is sufficiently short with respect to the display time td, and the responsiveness of the human eye Almost no problems arise. Accordingly, since each row is displayed at the timing shown in FIG. 2 by the read address counter 13, there is no difference in luminance. Also, there is no flickering of the display due to the scroll speed. Note that, during the operation of the read address counter 13, there is an instruction to write the display data DATA, and in the portion where the write address counter 14 operates, the selector 12 gives priority to the operation of the write address counter 14. As a result, new display data is updated. This writing time is equivalent to the rewriting time t wc, and even if the writing operation is interrupted, the display is not substantially disturbed because the allocation to the display time td is small. [Effects of the Invention] As described above, according to the present invention, flicker of display information and variation in luminance do not occur in the plasma display device of the flow character display type. In other words, in the plasma display device of the present invention,
Since the write address counter means and the read address counter means operable independently of each other in the screen memory are provided, flicker display and luminance caused by non-uniform display time and the like regardless of the moving speed of data display are provided. Can be eliminated, and a display with uniform brightness without flicker can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a plasma display device according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of the device of FIG. 1, FIG. 3 is a block diagram of a conventional plasma display device, FIG. 4 is an operation timing chart of the FIG. 3 apparatus. (Explanation of reference numerals) 1 ... I / O timing control circuit, 2 ... Screen memory, 3 ... P / S data converter, 4 ... Shift register, 5 ... Write address counter, 6 ... Internal clock circuit , 7: Row counter, 8: Decoder, 9: Y line driver, 10: X line driver, 11: Display unit, 12: Selector, 13: Read address counter, 14: Write address counter.

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-52-117029 (JP, A)                 JP-A-54-80621 (JP, A)                 JP-A-56-137396 (JP, A)

Claims (1)

(57) [Claims] In a plasma display device in which information to be displayed is written and stored in a storage unit, display information is read out from the storage unit, and the display information is displayed on the plasma display unit in a flowable manner. Writing address counter means for writing the display information to the storage unit, and a read address for reading the display information from the storage unit, which is always operable independently of the write address counter means. Only when an output signal from the write address counter and a write command signal indicating a request for writing the display information are simultaneously inputted during the operation of the counter and the read address counter, A part of the display information for which the write request has been made by operating the write address counter means prior to the operation of the address counter means Characterized by comprising a selector to switch to write to the storage unit, a plasma display device.