JP2003186445A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a display device which is reducible in power consumption. <P>SOLUTION: The display device comprises a VRAM 8 which stores image data of at least one picture, a held data switching circuit 3, holding circuit 1, and comparing circuit 2 which compare the latest image data of the pixel with the last image data of the pixel, a counter 4 which counts successive pieces of the same data according to the comparison result, and a VRAM readout control circuit 7, holding circuit 9, and output data switching circuit 10 which while reading image data out of the VRAM 8 when the latest data are different from the last data, stop the readout processing for the image data and hold image data being outputted as many times as they are successive when the data match each other. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image of a computer, for example, by using a display element having a pixel structure such as a liquid crystal, and in particular, realizes reduction of power consumption. The present invention relates to a display device capable of performing the above.

[0002]

2. Description of the Related Art A conventional display device will be described below. FIG. 7 is a diagram showing a configuration of a conventional display device described in Japanese Patent Laid-Open No. 10-240191. In FIG. 7, 101 is a video memory, and 102 and 103 are V
RAM 104, digital / analog (D /
A) a converter, 105 a read (R) address counter, 106 a row address decoder, 1
Reference numeral 07 is a transistor, 108 is a display unit, and 1
Reference numeral 09 is a pixel, 110 is an AND gate, and 11
1 is a column address decoder, 112 is a pixel address signal, and 113 is update data.

The video memory 101 is a VRAM 10 for storing display data stored in each pixel in the display section 108.
2 and a VRAM 103 that stores update data notifying that the pixels in the display unit 108 have been updated. When the total number of pixels of the display unit 108 is N, the address M of the VRAM 102 and VRAM 103 is
M> N. The number of bits per address is VRA.
M102 is 6 bits (which means that the display unit can display 64 gradations), and the VRAM 103 has one bit.

Here, the display data is written to the video memory 101 at the address of the VRAM 102 designated by the write address (W address), and at the same time, "1" is written in the VRAM 103 designated by the W address.
Is written.

On the other hand, the reading of data from the VRAM 102 and VRAM 103 is performed according to an instruction from the R address counter 105. For example, if the bit of VRAM 103 corresponding to the read address is "1", VRAM1
Since the display data read from 02 is updated, the AND gate 110 outputs R
The contents of the address counter 105 are output to the column address decoder 111 and the row address decoder 106. In addition,
In the figure, RCL represents a clock signal of the R address counter 105.

Then, the display data (digital value) read from the VRAM 102 is converted by the D / A converter 104 into analog value display data.

The high-order address information of the R address counter 105 output via the AND gate 110 is
The column address decoder 111 is notified, and one lower address information is notified to the row address decoder 106.
Then, the column address decoder 111 outputs the signal Rm based on the decoding result of the upper address information,
The on / off of the transistor 107 is controlled. For example, when it is on, the display data VID at that time is output to the column side drive terminal Xm. On the other hand, the row address decoder 10
In 6, the decoding result of the lower address information is output to the row side drive terminal Yn. As a result, the updated display data is written in the pixel 109 designated by each terminal Xm, Yn.

FIG. 8 is a time chart showing the operation of the display device. The clock signal RCL of a continuous signal is input to the R address counter 105, and the signal RES is generated at a specific cycle (for example, when the counter value is saturated). Here, the cycle of the signal RES corresponds to the display data update cycle.

Further, the RES resets the VRAM 103 (writes "0"). Here, when the specific address of the VRAM 102 specified by the W address is updated, "1" is written in the specific address of the corresponding VRAM 103, but on the other hand, when it is read by the R address. VR again by RES
The specific address of AM 103 is “0”.

The R address output from the R address counter 105 sequentially changes according to RCL. With this R address, the display data is read from the VRAM 102 and the update data is read from the VRAM 103.

When the update data read from the VRAM 103 is "1", the AND gate 110
The pixel address signal 1 of the display unit 108 is used as the R address data.
Output as 12. That is, the display pixels to be updated are a part of the whole. For example, the screen is updated in a word processor or the like only at the character portion. Therefore, when the above control is performed, the power consumption can be significantly reduced.

Further, if the data of a particular pixel is not updated for a predetermined time, the writing of data to this pixel will be interrupted for a long time. Therefore, for example, when the display element is liquid crystal, the electric charge accumulated in this pixel is gradually discharged, and as a result, the display image is gradually deteriorated.

FIG. 9 is a diagram showing the structure of a display device capable of preventing the above deterioration. In FIG. 9, 1
14 is a 60-counter that counts RES 60 times and 115 is a pulse. In addition, FIG.
10 is a time chart showing the operation of the display device shown in FIG. 9.

When the 60-count counter 114 counts 60 (when the counter value changes from 59 to 0), 1R
The pulse 115 is output with a width corresponding to the ES period. Pulse 11
5 is input to the AND gate 110, and this pulse 115
When is 1, the display unit 108 updates the display data for all pixels.

Specifically, when the RES cycle is 1/60 seconds, the cycle of the pulse 115, that is, the display unit 1
The cycle in which all the pixels of 08 are updated is 1 second. This is because when the display element is a liquid crystal, sufficient discharge of all pixels can be performed considering that the discharge path of the charge (display data) stored in the capacitance of each pixel and the impedance of the liquid crystal or the gate terminal of the transistor are extremely high. It can be called a cycle. That is, if all the pixels are updated in this cycle, the user does not recognize the display deterioration.

[0016]

As described above, in the conventional display device shown in FIG. 7, the VRAM 102 is used.
Although the power consumption can be significantly reduced by reducing the read access of the liquid crystal display device, on the other hand, for example, when the display element is a liquid crystal, the writing process is not performed on the pixels that are not updated, and the capacity of the liquid crystal is changed over time. There is a problem that the charged electric charge is discharged and the display is deteriorated.

Further, in the display device shown in FIG. 9 which solves the above problem, it is necessary to add a function for updating the data of all pixels, which leads to a complicated circuit and a large scale. There was a problem.

The present invention has been made in view of the above, and it is possible to reduce the number of accesses to the memory, and to reduce the power consumption while preventing the display deterioration without adding an extra circuit. The purpose of the present invention is to obtain an excellent display device.

[0019]

[Means for Solving the Problems]
In order to achieve the object, a display device according to the present invention is provided with a video memory (corresponding to a VRAM 8 in an embodiment described later) that stores at least one screen of image data, and further has a latest one pixel. Comparing means (corresponding to the held data switching circuit 3, the holding circuit 1 and the comparing circuit 2) for comparing the image data of one minute and the image data of one pixel before, and the same continuous data based on the comparison result. And a count means (corresponding to the counter 4) for counting the number of times (consecutive number information), and when the previous data and the latest data are different from each other, the image data is read from the video memory, and when they match Read-out control means (VRAM read-out control circuit 7, holding circuit 9 and output device) which stops the read-out processing of the image data and holds the image data being output for the continuous number of times. And equivalent) to data switching circuit 10, and further comprising a.

In the display device according to the next invention,
A video memory (corresponding to the VRAM 8) for storing at least one screen of image data is provided, and further, a comparison unit (retained data) for comparing the latest one-pixel image data with the immediately preceding one-pixel image data. Switching circuit 3, holding circuit 1,
(Corresponding to the comparing circuit 2), counting means (corresponding to the counter 4) for counting the number of consecutive identical data (consecutive count information) based on the comparison result, and reducing the lower several bits of the image data to reduce the bits. A merging unit (corresponding to the delay circuit 21 and the merging circuit 22) for merging the subsequent data and the consecutive number information, and switching control between the merged data and the image data based on a control signal, and either one of them is performed. A write control unit (corresponding to the write data switching circuit 23) for writing data in the video memory and the continuous count information in the merged data are read, and when it is determined that the same data is not continuous, the data is written from the video memory. After the merged data is read, on the other hand, when it is determined that the same data is continuous, the read processing of the merged data is stopped and Read control means for holding the merge after data being outputted over (VRAM read control circuit 7a,
Holding circuit 9 and output data switching circuit 10).

In the display device according to the next invention,
A video memory (corresponding to the VRAM 8) for storing at least one screen of image data is provided, and when operating in the low power consumption mode, the image data is read from the video memory and stored as the latest image data for one pixel. Comparing means (corresponding to the holding data switching circuit 3, the holding circuit 1, and the comparing circuit 2b) for comparing the image data of the immediately preceding pixel, and the number of consecutive same data based on the comparison result (continuous number information) ) Counting means (corresponding to the counter 4), and when the previous data and the latest data are different, the image data is read from the video memory, while when they match, the image data is read. The read control means (VRAM read control circuit 7b, which stops the processing and holds the image data being output for the continuous number of times).
Holding circuit 9 and output data switching circuit 10).

In the display device according to the next invention, the read control means counts the number of times the video memory is accessed in the one-screen display period, and when the access rate becomes equal to or more than a predetermined value, the continuous number information generation is performed. It is characterized in that all the processing relating to is stopped and thereafter all the data in the video memory is read out.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a display device according to the present invention will be described below in detail with reference to the drawings. In addition,
The present invention is not limited to the embodiments.

Embodiment 1. 1 is a diagram showing a configuration of a first embodiment of a display device according to the present invention. In FIG. 1, 1 is a holding circuit that holds image data for one display element, 2 is a comparison between the input image data value and the output value of the holding circuit 1, and if they match, "1" This is a comparison circuit that outputs “0” when they do not match.
Is a holding data switching circuit for selecting whether to keep the data of the holding circuit 1 in the next cycle or to switch to new data, and 4 continues counting while the output of the comparison circuit 2 is "1". A counter, 5 is a tag memory for storing the output of the counter 4 for one screen,
Reference numeral 6 is a write address generation circuit that determines to which address of the tag memory the match count is written, and reference numeral 7 is a VRAM read control circuit that controls reading from the video memory (hereinafter referred to as VRAM) and reading from the tag memory. 8 is a VRAM, 9 is a holding circuit that holds the read image data from the VRAM 8 for a matching period, and 10 is an output data switching circuit that selects the read output of the VRAM 8 or the output of the holding circuit 9. And 11
Is a liquid crystal display signal processing circuit that performs signal processing for driving the liquid crystal panel, and 12 is a liquid crystal panel.

The operation of the display device will be described below. First, image data and an input clock signal (hereinafter referred to as W-CLK) input from an external device (not shown)
Are supplied to the holding circuit 1. The holding circuit 1 is composed of a one-stage shift register and delays image data by a time corresponding to one clock cycle. The comparison circuit 2 compares the input image data with the output of the holding circuit 1. And
If both data values match, "1" is output. On the other hand, if they do not match, "0" is output. That is, here, comparison with the data of one pixel before is performed, and when they match,
It is determined that the same image data is continuous. In this case, the held data switching circuit 3 supplies the output of the holding circuit 1 again as it is, and the holding circuit 1 holds the same data for another clock cycle.

The counter 4 continues counting while the output of the comparison circuit 2 is "1". This makes it possible to count how many times the same data has been sent.

In the write address generation circuit 6, the tag memory 5 for recording the output of the counter 4 after the count is completed.
Determine the address of. The output of the counter 4 is stored in the tag memory 5 based on the address generated by the write address generation circuit 6. FIG. 2A is a diagram showing a state of the writing process. In this example, the first data is twice
3rd and 4th data is 1 time, 5th data is 4 times, 9
The th data is continuous 5 times.

The image data is also supplied to the VRAM 8. In the VRAM 8, a write address is internally generated based on W-CLK and the image data is stored. V
The read process from the RAM 8 is performed by internally generating a read address based on a read clock (hereinafter, referred to as R-CLK). Further, the reading process from the tag memory 5 is also performed by R-CLK, and its output is V
It is supplied to the RAM read control circuit 7.

The VRAM read control circuit 7 reads the number of consecutive times of the same data, and stops the reading from the VRAM 8 when the number of consecutive times is not "1".
Here, the read consecutive number is subtracted by 1 for each R-CLK, and the reading from the tag memory 5 is stopped until the consecutive number becomes "1".

In the holding circuit 1, the data output is delayed by one clock cycle by R-CLK. However, if the number of consecutive times held in the VRAM read control circuit 7 is other than "1", the delay operation is stopped, Holds the data.

In the output data switching circuit 10, when the number of consecutive times held by the VRAM read control circuit 7 is other than "1", the output of the holding circuit 9 is output at the next R-CLK timing.
In the case of "1", VRA is performed at the next R-CLK timing.
The read data of M8 is output. Figure 2
FIG. 6B is a diagram showing a state of the reading process. Here, when the output of the tag memory 5 is “1”, that is, 1
When it is different from the data before the pixel, the data in the VRAM 8 is read, and when the output of the tag memory 5 is other than "1", that is, when it is the same as the data one pixel before, the reading from the VRAM 8 is stopped.

Finally, in the liquid crystal display signal processing circuit 11,
Using the output of the output data switching circuit 10, the liquid crystal panel 12
Signal processing for driving the.

As described above, in the present embodiment, when writing the image data, the number of the same data continuously input is recorded, and during the period in which the same data continues, the reading from the memory is performed. Stop processing. As a result, low power consumption can be realized.

Embodiment 2. FIG. 3 is a diagram showing the configuration of the second embodiment of the display device according to the present invention. In FIG. 3, 7a is a V for controlling the read processing from the VRAM.
Reference numeral 21 is a RAM read control circuit, 21 is a delay circuit for image data, 22 is a merge circuit for writing a count value in a specific area of a data field of image data, and 23.
Is a merge circuit 22 output (image data in which a count value is written) or a write data switching circuit for selectively outputting image data. The same components as those in the first embodiment described above are designated by the same reference numerals and the description thereof will be omitted.

Here, the operation of the display device of the second embodiment will be described. Here, only the operation different from that of the first embodiment described above will be described.

In the present embodiment, as the writing processing to the VRAM 8, the normal mode for writing all the bits of the image data and the lower several bits of the image data are reduced, and the same number of consecutive times of the same data is reduced in the reduced empty memory area. The low power consumption mode for writing and is used properly. The mode switching process is performed using a power consumption mode switching signal supplied from the outside.

In the delay circuit 21, the output of the counter 4 is
In order to write in the VRAM 8 in synchronization with the corresponding image data, the image data is delayed by the time required for counting. In the delay circuit 21, the counter 4
Guarantee a delay of the maximum number of counts (maximum count value). As a result, the output of the counter 4 is written in the same VRAM address as the corresponding image data. Figure 4
FIG. 9 is a diagram showing a state of write processing according to the second embodiment.

The merge circuit 22 writes the count value in a specific area of the data field of the image data. That is, the lower several bits of the image data are reduced, and the continuous number of times of the same data (output from the counter 4) is written in the reduced specific area. The write data switching circuit 23 outputs the image data in the normal mode, and outputs the image data (the output of the merge circuit 22) in which the count value is written in the low power consumption mode.

The VRAM read control circuit 7a monitors the power consumption mode switching signal sent from the outside, and controls to read all the data in the VRAM 8 in the normal mode. V constantly
Select the output of RAM8. On the other hand, in the low power consumption mode, the VRAM read control circuit 7a reads the field of the number of consecutive times of the data read from the VRAM 8, and when the number of consecutive times is other than "1", the reading process from the VRAM 8 is stopped. To control. Note that the read continuous number is decremented by 1 for each R-CLK.

In the holding circuit 9, a delay of one clock cycle is added using R-CLK. For example, VRAM is used.
When the number of consecutive times held by the read control circuit 7a is other than "1", the delay operation is stopped and the data is held. The output data switching circuit 10 outputs the output of the holding circuit 9 when the number of consecutive times held by the VRAM read control circuit 7a is other than "1".
When it is "1", the read data of the VRAM 8 is output respectively.

As described above, in the present embodiment, the number of display bits (the number of colors, etc.) is reduced in order to realize low power consumption, and the unused memory area is used as the continuous image number recording area of the same image data. It was configured to do. This allows
Since the reading process can be stopped without using an additional memory, further reduction in power consumption can be promoted.

Embodiment 3. FIG. 5 is a diagram showing the configuration of the display device according to the third embodiment of the present invention. In FIG. 5, reference numeral 2b is a comparison circuit that compares the input image data value with the output value of the holding circuit 1 and outputs “1” if they match and “0” if they do not match, 6b
Is a write address generation circuit, 7b is a VRAM read control circuit that controls the read processing from the VRAM 8, and 31 is a data mask circuit that masks the lower bits of the image data by an arbitrary number of bits.

Here, the operation of the display device of the third embodiment will be described. Here, only the operation different from the above-described first and second embodiments will be described.

The VRAM read control circuit 7b detects the change from the normal mode to the low power consumption mode by monitoring the power consumption mode switching signal sent from the outside, and the one screen display period after the change is detected. Tag memory 5
It is determined that it is the rewriting period, and all the data in the VRAM 8 is read even in the low power consumption mode. At this time, the output data switching circuit 10 constantly selects the output of the VRAM 8.

In the low power consumption mode, the data mask circuit 31 receiving the image data read from the VRAM 8 masks the surplus bits determined based on the display bit number information, and outputs the output data of the data mask circuit 31. Is output to the comparison circuit 2b and the held data switching circuit 3.

The comparison circuit 2b and the write address generation circuit 6b detect the change from the normal mode to the low power consumption mode, and use the image data of the changed one screen display period, that is, the effective display bit (mask). Bits that are not written) are used to count the number of consecutive times of the same data,
The count result is controlled to be written in the tag memory 5.

After changing from the normal mode to the low power consumption mode, the VRAM read control circuit 7b operates in the same manner as in the second embodiment described above from the second screen display. That is, the number of consecutive times stored in the tag memory 5 is read out, and when the number of consecutive times is other than “1”, the reading process from the VRAM 8 is stopped. Note that the read continuous number is decremented by 1 for each R-CLK. Also,
Although the above processing has been described as a modified example of the first embodiment, the present invention is not limited to this and may be applied to the configuration of the second embodiment described above. In that case, the number of consecutive times of the same data is stored in the empty area of the VRAM 8 in the same procedure as in the second embodiment.

As described above, in the present embodiment, when the image data is temporarily stored and then changed to the low power consumption mode (for example, when each color data represented by 6 bits is switched to a 3 bit display). ), For the first one-screen display period, the currently stored image data is read and displayed. At this time, the read image data is masked based on the display bit number information, the number of consecutive times of the same data is counted using the masked image data, and the count result is stored. Then, after the display period of the second screen, the number of consecutive times stored in advance is read out, and when the number of consecutive times is other than “1”, the reading process of the stored image data is stopped. This allows
Further, it is possible to promote lower power consumption.

Fourth Embodiment FIG. 6 is a diagram showing the configuration of the display device according to the fourth embodiment of the present invention. In FIG. 6, reference numeral 7c indicates the tag memory 5 for controlling the reading of the VRAM 8.
Reference numeral 41 is a VRAM read control circuit added with a determination function for determining whether or not to use the information of 1., and 41 is a read number counter that counts how many times the VRAM 8 is accessed per screen.

Here, the operation of the display device of the fourth embodiment will be described. Here, the first and second embodiments described above are used.
Only the operations different from those of steps 1 and 3 will be described.

In the read number counter 41, the tag memory 5
In the next one-screen display period in which the VRAM read control circuit 7c has updated the
The number of times of accessing to AM8 is counted. In the VRAM read control circuit 7c, the counter 4, the tag memory 5, the write address generation circuit 6, the VRAM read control circuit 7c, when the access rate to the VRAM 8 becomes a certain value or more based on the read rate information given from the outside. Since the processing of each circuit such as the read number counter 41 and the like increases, and the power consumption increases, the "VRAM access method using the tag memory 5" is stopped and the "VRAM without using each circuit" is stopped.
8 method for reading all data ”. In this case, the output data switching circuit 10 constantly selects the output of the VRAM 8.

The VRAM read control circuit 7c uses the result of the read number counter 41 to calculate the access rate. In addition, the VRAM read control circuit 7c controls to completely stop the read operation of the tag memory 5 when an access method that does not use the tag memory 5 (a method of reading all data in the VRAM 8) is selected.

As described above, in the present embodiment, the number of accesses to the memory in which the image data is stored is counted during the display period for one screen, and when the access rate to the memory exceeds a certain value, From the method of the first embodiment described above,
It is configured to shift to a method of reading all the data in the memory. As a result, the power consumption can be controlled according to the number of accesses, so that the image can be always displayed in the optimum method. In addition, in the present embodiment, the read number counter 41 is applied to the configuration of the first embodiment (FIG. 1).
Not limited to this, the read number counter 41 is the same as that of the second embodiment.
Also applicable to 3 and 3.

[0054]

As described above, according to the present invention, when the image data is written, the number of the same data continuously input is recorded and the video is continuously recorded for the period in which the same data continues. The configuration is such that the reading process from the memory is stopped. As a result, it is possible to significantly reduce power consumption as compared with the conventional display device.

According to the next invention, the number of display bits (the number of colors, etc.) is reduced in order to realize low power consumption, and the unused memory area is used as the continuous number recording area of the same image data. . As a result, the reading process can be stopped without using the additional memory, and thus it is possible to further reduce power consumption.

According to the next invention, when the image data is temporarily stored and then changed to the low power consumption mode, the currently stored image data is read and displayed for the first one-screen display period. At this time, the read image data is used to count the number of consecutive times of the same data, and the count result is stored. Then, after the display period of the second screen, the number of consecutive times stored in advance is read out, and when the number of consecutive times is other than "1", for example,
The image data read processing is stopped. As a result, it is possible to further reduce the power consumption.

According to the next invention, the number of accesses to the video memory in which the image data is stored is counted in the display period for one screen, and when the access rate to the video memory exceeds a certain value, All the processes relating to the counting of the number of continuous times are stopped, and the system shifts to a method of reading all data from the video memory. As a result, it is possible to control power consumption according to the number of accesses, and thus it is possible to always display an image in an optimal method.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a display device according to the present invention.

FIG. 2 is a diagram showing a state of write / read processing according to the first embodiment.

FIG. 3 is a diagram showing a configuration of a second embodiment of a display device according to the present invention.

FIG. 4 is a diagram showing how write processing is performed in the second embodiment.

FIG. 5 is a diagram showing a configuration of a third embodiment of a display device according to the present invention.

FIG. 6 is a diagram showing a configuration of a display device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional display device.

FIG. 8 is a time chart showing the operation of the conventional display device.

FIG. 9 is a diagram showing a configuration of a conventional display device.

FIG. 10 is a time chart showing the operation of the conventional display device.

[Explanation of symbols]

1,9 holding circuit, 2,2b comparison circuit, 3 holding data switching circuit, 4 counter, 5 tag memory, 6,6b
Write address generation circuit, 7, 7a, 7b, 7c VR
AM read control circuit, 8 VRAM, 10 output data switching circuit, 11 liquid crystal display signal processing circuit, 12 liquid crystal panel, 21 image data delay circuit, 22 merge circuit, 2
3 write data switching circuit, 31 data mask circuit, 4
1 Read counter.

Continued front page    F term (reference) 2H093 NA15 NC27 NC29 NC71 ND39                 5C006 AA01 AF02 AF03 AF04 AF13                       AF44 AF45 AF51 AF53 AF61                       AF69 BB11 BC16 BF02 BF14                       BF22 BF24 FA47                 5C080 AA10 BB05 DD26 EE19 GG07                       GG08 GG12 JJ02 JJ04

Claims (4)

[Claims] 1. A display device comprising a video memory for storing at least one screen of image data, and a comparing means for comparing the latest image data of one pixel with the image data of one previous pixel. Counting means for counting the number of consecutive identical data (consecutive number information) based on the comparison result, and reading the image data from the video memory when the previous data and the latest data are different, And a reading control unit that stops the reading process of the image data and holds the image data being output for the continuous number of times when they match each other. 2. A display device comprising a video memory for storing at least one screen of image data, and a comparing means for comparing the latest one pixel of image data with the immediately preceding one pixel of image data. A count means for counting the number of consecutive identical data (consecutive number information) based on the comparison result, and a merge for reducing the lower several bits of the image data and merging the bit-reduced data and the consecutive number information Means for controlling switching between the merged data and the image data based on a control signal and writing either one of the data in a video memory, and reading the number of consecutive times information in the merged data, When it is determined that the same data is not continuous, the merged data is read from the video memory, while it is determined that the same data is continuous. The case, the display device stops reading processing of the data after the merge, characterized in that it comprises a read control means for holding the merge after data being outputted over the number of successive minutes. 3. A display device having a video memory for storing at least one screen of image data, and when operating in a low power consumption mode, the image data is read out from the video memory and the latest one pixel of image data is read. And a comparison means for comparing the image data of one pixel before one with the previous one, a counting means for counting the number of consecutive identical data (continuous number information) based on the comparison result, and the previous data. When the latest data is different, the image data is read from the video memory, and when the latest data is the same, the reading process of the image data is stopped and the image data being output is retained for the continuous number of times. A display device comprising: 4. The read control means counts the number of times the video memory is accessed during one screen display period, and when the access rate is equal to or higher than a predetermined value, stops all the processes related to the continuous number information generation. 4. The display device according to claim 1, 2 or 3, wherein all the data in the video memory is read out thereafter.