JP4164966B2 - MPEG image display control method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an MPEG image display control method and apparatus for performing image display control by decoding an MPEG (Moving Picture Experts Group) stream.
[0002]
[Prior art]
FIG. 13 is a block circuit diagram showing the main part of an example of a conventional MPEG image display apparatus. In FIG. 13, 1 is a display, 2 is a conventional MPEG image display control device that decodes an MPEG stream and performs image display control. In the MPEG image display control device 2, 3 is an MPEG decoder that decodes the MPEG stream, 4 Reference numerals -0, 4-1, and 4-2 denote frame memories for storing the decoded image data output from the MPEG decoder 3.
[0003]
Reference numeral 5 denotes a distribution circuit that is controlled by a distribution control signal supplied from the MPEG decoder 3 and distributes the decoded image data output from the MPEG decoder 3 to one of the frame memories 4-0, 4-1, 4-2. 6 is a selector that is controlled by a select control signal supplied from the MPEG decoder 3 and selects one of the frame memories 4-0, 4-1, and 4-2, and outputs decoded image data output from the selected frame memory. , 7 is a display control unit that, when the decoded image data output from the selector 6 is display image data, inputs this and performs image display control on the display 1.
[0004]
FIG. 14 is a timing chart showing an operation example of the conventional MPEG image display apparatus shown in FIG. 13. FIG. 14A is a decoded image output from the MPEG decoder 3, FIG. 14B is a display image displayed on the display 1, and FIG. Is a decoded image stored in the frame memories 4-0 to 4-2, and FIG. 14D shows a memory map of the frame memory 4-2 at time TA. In this operation example, the MPEG decoder 3 performs decoding in the order of I2 image → B0 image → B1 image → P6 image → B3 image → B4 image → B5 image → P10 image, and in the display 1, B0 image → B1 image → Display is performed in the order of I2 image → B3 image → B4 image → B5 image.
[0005]
[Problems to be solved by the invention]
In the conventional MPEG image display apparatus shown in FIG. 13, the decoding process of the MPEG stream and the display process of the decoded image are not synchronized in units of frames, and the display image data is decoded to the frame memory from which the display image data is read out. There are cases where image data must be written. For example, in the operation example shown in FIG. 14, when B4 image data is output from the MPEG decoder 3, the frame memories 4-0 and 4-1 are reference image data to be held as valid data, respectively. Since the I2 image data and the P6 image data are stored, the B4 image data cannot be written in the frame memories 4-0 and 4-1, but the B3 image data is stored and the B3 image data is actually read out. The B4 image data must be overwritten on the frame memory 4-2.
[0006]
For example, as shown in FIG. 15, when an error occurs in the B4 image data being decoded in the MPEG decoder 3, what is displayed next to the currently displayed B3 image is as follows: There are a method of displaying a B4 image with no change, (2) a method of displaying a currently displayed B3 image, and (3) a method of displaying an I2 image or a P6 image held as a reference image. However, the method (1) is inconvenient in displaying a B4 image including an error, and the method (2) is inconvenient in displaying a B3 image overwritten with the B4 image. The method 3) is disadvantageous in that it displays an image having a contradiction in the time relationship of the display image.
[0007]
As described above, in the conventional MPEG image display device including the conventional MPEG image display control device 2 shown in FIG. 13, when an error occurs in the decoded image, sufficient error concealment processing cannot be performed, and the display There is a problem in that the disturbance of the display image in 1 cannot be made inconspicuous. In particular, in broadcast media, since an MPEG stream is transmitted by radio waves, an error in which a bit string becomes abnormal due to noise is likely to occur. For this reason, error concealment processing is particularly important.
[0008]
In view of the above, the present invention provides an MPEG image that can prevent a display image from becoming disturbed by a simple error concealment process when an error occurs in decoded image data in an MPEG decoder. It is an object to provide a display control method and apparatus.
[0009]
[Means for Solving the Problems]
The MPEG image display control method of the present invention includes a step of decoding an MPEG stream so that one frame of encoded image data is decoded within one frame display period; Obtained by decoding Decode image data in frame units Of multiple frame memories Including writing to the frame memory that stores invalid data. The decoding process of the encoded image data of one frame starts after the image header of the corresponding frame and before the image data of the corresponding frame, and stops after the image header of the next frame and before the image data of the next frame. Then, based on the result of the decoding process of the image header of the next frame, the plurality of frame memories are arranged such that a display image data storage frame memory, a decoded image data storage frame memory, and a reference image data storage frame memory exist simultaneously. And switching to one of the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory. That's it.
[0010]
In the MPEG image display control method of the present invention, it is assumed that one frame of encoded image data is decoded within one frame display period, and the decoding process and the display process are synchronized in units of frames. In addition, the decoded image data output from the MPEG decoder is written in units of frames in a frame memory storing invalid data, and the frame memory storing decoded image data that is the base data of the currently displayed image In addition, the decoded image data output from the MPEG decoder is not written in the frame memory storing the decoded image data to be held as the reference image data. As a result, when an error occurs in the decoded image data in the MPEG decoder, the currently displayed image can be displayed repeatedly.
[0011]
An MPEG image display control apparatus according to the present invention includes an MPEG decoder that decodes an MPEG stream so as to decode one frame of encoded image data within one frame display period, a display image data storage frame memory, and decoded image data. A plurality of frames that can be switched to any one of the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory so that the storage frame memory and the reference image data storage frame memory exist simultaneously. Equipped with memory The MPEG decoder starts decoding the encoded image data of one frame after the image header of the corresponding frame and before the image data of the corresponding frame, and after the image header of the next frame, Based on the result of decoding the image header of the next frame, the plurality of frame memories are divided into the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data. Switch to one of the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory so that the storage frame memory exists simultaneously. That's it.
[0012]
In the MPEG image display control apparatus of the present invention, one frame of encoded image data is decoded within one frame display period, and the decoding process and the display process are synchronized in units of frames. In addition, by assigning a frame memory storing invalid data as a decoded image data storage frame memory among a plurality of frame memories, a frame storing decoded image data which is the basic data of the currently displayed image It is possible not to write the decoded image data output from the MPEG decoder in the memory or the frame memory storing the decoded image data to be held as reference image data. As a result, when an error occurs in the decoded image data in the MPEG decoder, the currently displayed image can be displayed repeatedly.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The MPEG image display control method according to the first to fourth embodiments of the present invention and the MPEG image display control apparatus according to an embodiment of the present invention will be described below with reference to FIGS.
[0014]
First Embodiment of MPEG Image Display Control Method of the Present Invention. FIG. 1 and FIG.
The first embodiment of the MPEG image display control method according to the present invention uses four frame memories M0, M1, M2, and M3. In the MPEG decoder, one frame of encoded image data within one frame display period. The image display control is performed in such a manner that the MPEG stream is decoded so as to be decoded, and one frame of decoded image data output from the MPEG decoder is written in the frame memory storing invalid data. It is included in the process.
[0015]
FIG. 1 is a timing chart showing a first specific example of the first embodiment of the MPEG image display control method of the present invention. FIG. 1A is a decoded image output from the MPEG decoder, and FIG. 1B is a display image displayed on the display. FIG. 1C shows decoded images stored in the frame memories M0 to M3.
[0016]
In the first specific example shown in FIG. 1, the MPEG decoder performs decoding processing in the order of I2 image → B0 image → B1 image → P6 image → B3 image → B4 image → B5 image → P10 image. Display is performed in the order of image → B1 image → I2 image → B3 image → B4 image → B5 image.
[0017]
Moreover, the decoding processing of the B1 image, P6 image, B3 image, B4 image, B5 image, and P10 image after the decoding processing of the I2 image and the B0 image that need to be performed prior to the display processing, respectively, is the B0 image. , B1 image, I2 image, B3 image, B4 image, and B5 image are executed in synchronism with each frame.
[0018]
Further, the I2 image data is written in the frame memory M0 that stores the initial value that is invalid data, and the B0 image data is written in the frame memory M1 that stores the initial value that is invalid data. The B1 image data is written in the frame memory M2 that stores the initial value that is invalid data, and the P6 image data is written in the frame memory M1 that stores the B0 image data that is displayed invalid data.
[0019]
The B3 image data is written to the frame memory M2 that stores the B1 image data that is the invalid data that has been displayed, and the B4 image data is written to the frame memory M3 that stores the initial value that is the invalid data. The B5 image data is written in the frame memory M2 that stores the displayed invalid data B3 image data, and the P10 image data is stored in the frame memory M0 that stores the displayed and referenced invalid data I2 image data. Has been written.
[0020]
Therefore, for example, as shown in FIG. 2, when an error occurs in the B4 image data in the MPEG decoder, after the display of the B3 image is finished, it is based on the B3 image data that is completely retained without being overwritten. Thus, the B3 image can be repeated. In this case, the B5 image data output from the MPEG decoder during the repeat display of the B3 image is written in the frame memory M3 that stores the B4 image data that is invalid data.
[0021]
Thus, according to the first embodiment of the MPEG image display control method of the present invention, the MPEG decoder decodes one frame of encoded image data within one frame display period and outputs the decoded image data from the MPEG decoder. Since the image data is written in the frame memory storing invalid data, when an error occurs in the decoded image data in the MPEG decoder, a simple error concealment is displayed in which the currently displayed image is repeatedly displayed. By performing the processing, it is possible to make the display image not conspicuous.
[0022]
Second Embodiment of MPEG Image Display Control Method of the Present Invention. FIG. 3 to FIG.
The second embodiment of the MPEG image display control method of the present invention is the same as the first embodiment of the MPEG image display control method of the present invention, and the decoding process of one frame of encoded image data is performed by the image header (Picture Header) of the corresponding frame. Thereafter, it starts before the image data (Picture Data) of the corresponding frame, and stops after the image header of the next frame and before the image data of the next frame.
[0023]
FIG. 3 is a timing chart showing a specific example of the second embodiment of the MPEG image display control method of the present invention. FIG. 3A is a decoded image output from the MPEG decoder, FIG. 3B is a display image displayed on the display, and FIG. Reference numeral 3C denotes a decoded image stored in the frame memories M0 to M3.
[0024]
DEC means that the frame memory is assigned as a decoded image data storage frame memory, DISP means that the frame memory is assigned as display image data as a storage frame memory, and BWD indicates that the frame memory is assigned. FWD means that the frame memory is assigned as the backward reference image data storage frame memory, and FWD means that the frame memory is assigned as the forward reference image data storage frame memory.
[0025]
The frame image allocated as the decoded image data storage frame memory stores the decoded image data output from the MPEG decoder, and the decoded image data stored in the frame memory allocated as the display image data storage frame memory is Decoded image data that is treated as display image data and stored in a frame memory assigned as a backward reference image data storage frame memory is treated as backward reference image data, and a frame memory assigned as a forward reference image data storage frame memory The decoded image data stored in is treated as forward reference image data.
[0026]
In the specific example shown in FIG. 3, the B1 image stream image data and the P6 image stream image header (PHD) are decoded at the B0 image display frame, and the P6 image stream image data and the B3 image at the B1 image display frame. The image header of the stream is decoded. In the I2 image display frame, the image data of the B3 image stream and the image header of the B4 image stream are decoded. In the B3 image display frame, the image data of the B4 image stream and the B5 image stream are decoded. The image header is decoded.
[0027]
FIG. 4 shows an example of reference image data assignment operation. Reference image data used by the MPEG decoder for decoding is determined by the image type of the decoded image. For example, when the decoded image is a B image, the transition of the reference image assignment does not occur, but when the decoded image is an I image or a P image, the decoded image assigned as the backward reference image data (BWD). Allocation changes occur, such as when data transitions to forward reference image data (FWD). As described above, in the MPEG decoder, it is not possible to determine whether the reference image data is assigned to the backward reference image data or the forward reference image data unless the image type of the decoded image is known.
[0028]
Therefore, FIG. 5 schematically shows the structure of the MPEG stream. Since the 1-frame image stream has a structure in which the image data follows the image header, the decoding process of the 1-frame image stream is performed as 1 When synchronized with the frame display process, for example, as shown in FIG. 6, at the end of the display of the B0 image, the image header of the P6 image that is the next decoded image is not decoded, and the next decoded image is P6. Since it is not known to be an image, I2 image data cannot be assigned at the timing of changing the display frame assignment from the B0 image to the B1 image, and only after decoding the image header of the P6 image stream. , I2 image data cannot be assigned.
[0029]
At the end of the display of the B1 image, the image header of the B3 image, which is the next decoded image, has not been decoded, and it is not known that the next decoded image is the B3 image, so the B1 image is changed to the I2 image. P6 image data cannot be allocated at the timing of the display frame allocation change, and P6 image data cannot be allocated unless after decoding of the image header of the B3 image stream. In order to avoid such inconvenience, extremely complicated control is required.
[0030]
However, in the specific example shown in FIG. 3, when the B0 image is displayed, since the image header of the P6 image stream is decoded after the image data of the B1 image stream, it is found that the image to be decoded next is the P6 image. However, there is no inconvenience that the I2 image data cannot be assigned at the timing of the change in the display frame assignment from the B0 image to the B1 image, and when the B1 image is displayed, the B3 image is displayed after the image data of the P6 image stream. Since the image header of the image stream is decoded, there is no inconvenience that the P6 image data cannot be allocated at the timing of the display frame allocation change from the B1 image to the I2 image.
[0031]
As described above, according to the second embodiment of the MPEG image display control method of the present invention, in the first embodiment of the MPEG image display control method of the present invention, the decoding process of one frame of encoded image data is performed for the corresponding frame. Since it starts after the image header and before the image data of the corresponding frame and stops after the image header of the next frame and before the image data of the next frame, the MPEG image display control method of the first embodiment of the present invention In addition to obtaining the same operational effects, it is possible to avoid the inconvenience that reference image data cannot be allocated at the timing of display frame allocation change without complicated control.
[0032]
Third Embodiment of MPEG Image Display Control Method of the Present Invention FIG. 7
According to the third embodiment of the MPEG image display control method of the present invention, in the first embodiment of the MPEG image display control method of the present invention, the decoding process of one frame of encoded image data is not completed within one frame display period. In this case, the currently displayed frame image is repeatedly displayed.
[0033]
FIG. 7 is a timing chart showing a specific example of the third embodiment of the MPEG image display control method of the present invention. FIG. 7A shows a decoded image output from the MPEG decoder, and FIG. 7B shows a display image displayed on the display. In the specific example shown in FIG. 7, since the decoding of the B3 image is not completed at the end of the display of the I2 image, the repeat display of the I2 image is performed, and the B4 image decoding process and the B3 performed next are performed. Synchronization with image display processing is taken.
[0034]
As described above, according to the third embodiment of the MPEG image display control method of the present invention, in the first embodiment of the MPEG image display control method of the present invention, decoding of encoded image data of one frame within one frame display period is performed. If the processing is not completed, the currently displayed frame image is displayed repeatedly, so that the same operational effects as in the first embodiment of the MPEG image display control method of the present invention can be obtained. Even when decoding of one frame of encoded image data does not end within one frame display period due to delay of the input stream or the like, synchronization between the decoding processing and the display processing is performed without performing inconvenient image display. Can take.
[0035]
Fourth Embodiment of MPEG Image Display Control Method of the Present Invention FIG.
In the fourth embodiment of the MPEG image display control method of the present invention, when repeat display is performed in the first embodiment of the MPEG image display control method of the present invention, the decoding process is performed until the display switching timing after the end of repeat display. Is to wait.
[0036]
FIG. 8 is a timing chart showing a specific example of the fourth embodiment of the MPEG image display control method of the present invention. FIG. 8A shows a decoded image output from the MPEG decoder, and FIG. 8B shows a display image displayed on the display. In the specific example shown in FIG. 8, an example in which the I2 image is repeatedly displayed is shown, and the decoding process of the B4 image is waited until the display switching timing after the end of the I2 image repeat display. Note that the frame memory allocation is not switched when the repeat display is performed.
[0037]
Thus, according to the fourth embodiment of the MPEG image display control method of the present invention, when repeat display is performed in the first embodiment of the MPEG image display control method of the present invention, Since the decoding process is waited until the display switching timing, the same effects as the first embodiment of the present invention can be obtained, and a repeat display instruction included in the MPEG stream or an external display stop instruction, etc. Thus, even when repeat display is performed, the decoding process and the display process can be synchronized.
[0038]
Embodiment of MPEG Image Display Control Device of the Present Invention FIG.
FIG. 9 is a block circuit diagram showing the main part of an MPEG image display apparatus provided with an embodiment of the MPEG image display control apparatus of the present invention. In FIG. 9, 8 is a display, and 9 is an image display by decoding an MPEG stream. 1 is an embodiment of an MPEG image display control apparatus according to the present invention for performing control.
[0039]
In the ninth embodiment of the MPEG image display control apparatus of the present invention, reference numeral 10 denotes a process of decoding one frame of encoded image data within one frame display period, and a process of decoding one frame of encoded image data. Is an MPEG decoder that decodes an MPEG stream so that it starts after the image header of the corresponding frame and before the image data of the corresponding frame, and stops after the image header of the next frame and before the image data of the next frame. .
[0040]
Reference numerals 11-0 to 11-3 denote frame memories for storing decoded image data output from the MPEG decoder 10 in units of frames. Reference numeral 12 denotes decoded image data output from the MPEG decoder 10 to frame memories 11-0 to 11-. The distribution operation is controlled by a decoded image data storage frame memory designation signal dec output from the MPEG decoder 10.
[0041]
A selector 13 selects one of the frame memories 11-0 to 11-3 and outputs decoded image data output from the selected frame memory. A forward reference image data output from the MPEG decoder 10 is stored. A selector that selects the frame memory designation signal fwd, the backward reference image data storage frame memory designation signal bwd, or the display image data storage frame memory designation signal disp and supplies the selected signal to the selector 13 as a select control signal. When the decoded image data to be output is display image data, it is a display control unit that inputs this and controls image display on the display 8.
[0042]
In the MPEG decoder 10, reference numeral 16 designates each of the frame memories 11-0 to 11-3 as a decoded image data storage frame memory, a forward reference image data storage frame memory, or a backward reference image data storage frame memory. A frame memory that outputs a frame memory allocation switching timing signal CHANGE for controlling the switching timing of the frame memory allocation to be allocated to the display image data storage frame memory in synchronization with the frame synchronization signal FSYNC supplied from the display control unit 15 It is an allocation switching timing signal generation unit.
[0043]
The frame memory allocation switching timing signal generation unit 16 includes a decoding delay detection unit 17 that detects a case where decoding processing of encoded image data of one frame is not completed within one frame display period, and a repeat included in the MPEG stream A display repeat control unit 18 that controls display repeat according to a display instruction or an external display stop instruction is provided. When the decode delay detection unit 17 detects a decode delay or the display repeat control unit 18 instructs display repeat. In this case, the frame memory allocation switching timing signal CHANGE is masked.
[0044]
Reference numeral 19 denotes a frame memory allocation control unit that controls the allocation of the frame memories 11-0 to 11-3 in synchronization with the frame memory allocation switching timing signal CHANGE. Reference numeral 20 denotes a decoded image that designates the decoded image data storage frame memory. Data storage frame memory designation register. The contents of the decoded image data storage frame memory designation register 20 are supplied to the distribution circuit 12 as a decoded image data storage frame memory designation signal dec.
[0045]
The decoded image data storage frame memory designation register 20 writes the decoded image data output from the MPEG decoder 10 into the frame memory storing invalid data among the frame memories 11-0 to 11-3. Its contents are set.
[0046]
Further, 21 is a forward reference image data storage frame memory designation register for designating a forward reference image data storage frame memory, 22 is a backward reference image data storage frame memory designation register for designating a backward reference image data storage frame memory, and 23 is a display image. It is a display image data storage frame memory designation register for designating a data storage frame memory.
[0047]
Here, the content of the forward reference image data storage frame memory designation register 21 is input to the selector 14 as the forward reference image data storage frame memory designation signal fwd, and the content of the backward reference image data storage frame memory designation register 22 is the backward reference image data. The storage frame memory designation signal bwd is input to the selector 14, and the contents of the display image data storage frame memory designation register 23 are input to the selector 14 as the display image data storage frame memory designation signal disp.
[0048]
Reference numeral 24 denotes a memory control unit that controls which of the forward reference image data, backward reference image data, and display image data should be output from the frame memories 11-0 to 11-3. When the control unit 24 is to output the forward reference image data, the forward reference image data storage frame memory designation signal fwd is selected. When the memory control unit 24 is to output the backward reference image data, the backward reference image data is output. When the reference image data storage frame memory designation signal bwd is selected and the memory control unit 24 is to output the display image data, the display image data storage frame memory designation signal disp is selected.
[0049]
When the forward reference image data storage frame memory designation signal fwd is supplied, the selector 13 selects the output of the frame memory designated by the forward reference image data storage frame memory designation signal fwd, and the rear reference image data storage frame When the memory designation signal bwd is supplied, the output of the frame memory designated by the backward reference image data storage frame memory designation signal bwd is selected, and when the display image data storage frame memory designation signal disp is supplied, the display image is displayed. The output of the frame memory designated by the data storage frame memory designation signal disp is selected.
[0050]
In the MPEG image display apparatus including the ninth embodiment of the MPEG image display control apparatus of the present invention shown in FIG. 9 configured as described above, the MPEG decoder 10 can store one frame of encoded image data within one frame display period. In order to perform the decoding process, the decoding process of the encoded image data of one frame starts after the image header of the corresponding frame and before the image data of the corresponding frame, and after the image header of the next frame, the image of the next frame The MPEG stream is decoded so as to stop before data, and the decoded image data output from the MPEG decoder 10 is stored in the frame memory storing invalid data among the frame memories 11-0 to 11-3. Written.
[0051]
That is, according to the ninth embodiment of the MPEG image display control apparatus of the present invention, the first and second embodiments of the MPEG image display control method of the present invention can be executed. When no error occurs in the image data, for example, the operation is performed as shown in FIG. 10. In the MPEG decoder 10, for example, when an error occurs in the B4 image, as shown in FIG. The image is repeatedly displayed.
[0052]
10A and 11A are frame synchronization signals FSYNC output from the display control unit 15, FIGS. 10B and 11B are frame memory allocation switching timing signals CHANGE output from the frame memory allocation switching timing signal generation unit 16, and FIG. 10C. 11C is a decoded image output from the MPEG decoder 10, FIGS. 10D and 11D are allocation states of the frame memories 11-0 to 11-3, and FIGS. 10E and 11E are stored in the frame memories 11-0 to 11-3. The decoded image is shown.
[0053]
Further, in the ninth embodiment of the MPEG image display control apparatus of the present invention, when the decoding process of one frame of encoded image data is not completed within one frame display period, the decoding delay detection unit 17 detects this. As a result, the frame memory allocation switching timing signal CHANGE is masked, so that the frame memory allocation is not switched.
[0054]
In addition, when there is a repeat display instruction included in the MPEG stream or a display stop instruction from the outside, the display repeat control unit 18 instructs display repeat. The frame memory allocation switching timing signal CHANGE is masked, and the frame memory allocation is not switched.
[0055]
That is, according to the ninth embodiment of the MPEG image display control apparatus of the present invention, the third and fourth embodiments of the MPEG image display control method of the present invention can be executed. If the decoding process of the B1 image data is not completed or if there is a repeat display instruction for the I2 image, the operation is performed as shown in FIG. 12, for example.
[0056]
12A shows the frame synchronization signal FSYNC output from the display control unit 15, FIG. 12B shows the decode delay detection signal DELAY output from the decode delay unit 17, and FIG. 12C shows the display repeat instruction output from the display repeat control unit 18. 12D is a frame memory allocation switching timing signal CHANGE output from the frame memory allocation switching timing signal generator 16, FIG. 12E is a decoded image output from the MPEG decoder 10, and FIG. 12F is a frame memory 11-0 to 11-11. FIG. 12G shows decoded images stored in the frame memories 11-0 to 11-3.
[0057]
As described above, according to the ninth embodiment of the MPEG image display control apparatus of the present invention, the first to fourth embodiments of the MPEG image display control method of the present invention can be executed. In the MPEG decoder 10, when an error occurs in the decoded image data, a simple error concealment process of displaying the currently displayed image repeatedly may be performed so as to make the display image not conspicuous. (2) It is possible to avoid the inconvenience that reference image data cannot be allocated at the timing of display frame allocation change without performing complicated control, and (3) reasons such as delay of input stream Thus, when the decoding process of one frame of encoded image data is not completed within one frame display period By performing repeat display, it is possible to synchronize the decoding process and the display process without performing inconvenient image display. (4) Repeat display instruction included in the MPEG stream or external display stop Even when repeat display is performed by an instruction or the like, the decoding process and the display process can be synchronized.
[0058]
Here, when the contents of the MPEG image display control method and apparatus of the present invention are organized, the MPEG image display control method and apparatus of the present invention includes at least the following MPEG image display control method and apparatus.
[0059]
[1] In the MPEG decoder, the MPEG stream is decoded so that one frame of the encoded image data is decoded within one frame display period, and the decoded image data output from the MPEG decoder is frame by frame. An MPEG image display control method comprising a step of writing into a frame memory storing invalid data.
[0060]
[2] In the MPEG image display control method according to [1], the decoding process of the encoded image data of one frame starts after the image header of the corresponding frame and before the image data of the corresponding frame. An MPEG image display control method characterized by stopping after the image header before the image data of the next frame.
[0061]
[3] In the MPEG image display control method according to [1], if the decoding process of the encoded image data of one frame is not completed within one frame display period, the currently displayed frame image is An MPEG image display control method, wherein repeat display is performed and the next decoding process is not performed until the next display switching is performed.
[0062]
[4] In the MPEG image display control method according to [1], when repeat display is performed, the decoding process is waited until display switching timing after the end of repeat display. .
[0063]
[5] An MPEG decoder that decodes an MPEG stream so as to decode one frame of encoded image data within one frame display period, a display image data storage frame memory, a decoded image data storage frame memory, and first, Switch to one of the display image data storage frame memory, the decoded image data storage frame memory, and the first and second reference image data storage frame memories so that a second reference image data storage frame memory exists simultaneously. An MPEG image display control apparatus comprising a plurality of frame memories that can be allocated.
[0064]
[6] In the MPEG image display control device according to [5], the MPEG decoder starts the decoding process of the encoded image data of the one frame after the image header of the corresponding frame and before the image data of the corresponding frame. And an MPEG image display control apparatus which stops after the image header of the next frame and before the image data of the next frame.
[0065]
[7] In the MPEG image display control device according to [5], the MPEG decoder displays the current image when the decoding process of the encoded image data of one frame has not been completed within one frame display period. An MPEG image display control apparatus, wherein a frame image being displayed is repeatedly displayed, and the next decoding process is not performed until the next display switching is performed.
[0066]
[8] In the MPEG image display control device according to [5], in the case of performing repeat display, the MPEG decoder waits for decoding processing until display switching timing after the end of repeat display. MPEG image display control device.
[0067]
【The invention's effect】
As described above, according to the MPEG image display control method of the present invention, the decoding process and the display process can be synchronized in units of frames, and the decoded image data output from the MPEG decoder is stored as invalid data. In the MPEG decoder, it is possible to prevent the decoded image data from being written in the frame memory storing the decoded image data which is the basic data of the currently displayed image. When an error occurs, a simple error concealment process in which the currently displayed image is repeatedly displayed can be made inconspicuous.
[0068]
In addition, according to the MPEG image display control apparatus of the present invention, the MPEG image display control method of the present invention is executed, and when an error occurs in the decoded image data in the MPEG decoder, the currently displayed image is repeatedly displayed. By performing such simple error concealment processing, it is possible to make the display image not conspicuous.
[Brief description of the drawings]
FIG. 1 is a timing chart showing a first specific example of a first embodiment of an MPEG image display control method of the present invention.
FIG. 2 is a timing chart showing a second specific example of the first embodiment of the MPEG image display control method of the present invention.
FIG. 3 is a timing chart showing a specific example of the second embodiment of the MPEG image display control method of the present invention.
FIG. 4 is a timing chart showing an example of an operation of assigning reference image data.
FIG. 5 is a diagram schematically showing the structure of an MPEG stream.
FIG. 6 is a timing chart for explaining problems that occur when decoding processing of a one-frame image stream is performed in synchronization with one-frame display processing.
FIG. 7 is a timing chart showing a specific example of the third embodiment of the MPEG image display control method of the present invention.
FIG. 8 is a timing chart showing a specific example of the fourth embodiment of the MPEG image display control method of the present invention.
FIG. 9 is a block circuit diagram showing a main part of an MPEG image display apparatus provided with an embodiment of the MPEG image display control apparatus of the present invention.
10 is a timing chart showing a first operation example of the MPEG image display apparatus shown in FIG. 9;
11 is a timing chart showing a second operation example of the MPEG image display apparatus shown in FIG. 9;
12 is a timing chart showing a third operation example of the MPEG image display apparatus shown in FIG. 9. FIG.
FIG. 13 is a block circuit diagram showing a main part of an example of a conventional MPEG image display apparatus.
14 is a timing chart showing an operation example of the conventional MPEG image display apparatus shown in FIG.
FIG. 15 is a timing chart for explaining problems of the conventional MPEG image display control device shown in FIG. 13;
[Explanation of symbols]
(Fig. 9)
20 Decoded image data storage frame memory specification register
21 Forward reference image data storage frame memory specification register
22 Back reference image data storage frame memory specification register
23 Display image data storage frame memory specification register
dec Decoded image data storage frame memory designation signal
fwd Forward reference image data storage frame memory designation signal
bwd Back reference image data storage frame memory designation signal
disp Display image data storage frame memory designation signal
FSYNC frame sync signal
CHANGE Frame memory allocation switching timing signal

Claims (6)

A process of decoding an MPEG stream so that one frame of encoded image data is decoded within one frame display period;
Writing the decoded image data obtained by the decoding process in units of frames into a frame memory storing invalid data among a plurality of frame memories ;
The decoding process of the encoded image data of one frame starts after the image header of the corresponding frame and before the image data of the corresponding frame, stops after the image header of the next frame and before the image data of the next frame ,
Based on the result of the decoding process of the image header of the next frame, the plurality of frame memories are arranged such that a display image data storage frame memory, a decoded image data storage frame memory, and a reference image data storage frame memory exist simultaneously. The MPEG image display control method, wherein the display image data storage frame memory, the decoded image data storage frame memory, or the reference image data storage frame memory is switched . 2. The MPEG image display control method according to claim 1, further comprising a step of repeatedly displaying the currently displayed decoded image data when an error occurs in the decoded image data. An MPEG decoder that decodes an MPEG stream so as to decode one frame of encoded image data within one frame display period;
The display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory so that a display image data storage frame memory, a decoded image data storage frame memory, and a reference image data storage frame memory exist simultaneously. With multiple frame memories that can be switched to
The MPEG decoder starts decoding the encoded image data of one frame after the image header of the corresponding frame and before the image data of the corresponding frame. After the image header of the next frame, the image data of the next frame Based on the result of decoding the image header of the next frame, the plurality of frame memories are divided into the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame. An MPEG image display control device , wherein the display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory are switched so that the memory exists simultaneously . A decoder circuit that decodes the MPEG stream and outputs decoded image data;
A plurality of frame memories for storing the decoded image data;
Frame by frame the decoded image data output from the decoder circuit, among the plurality of frame memories, and a control circuit for writing to the frame memory storing the invalid data,
The decoder circuit decodes one frame of encoded image data within one frame display period, and performs the decoding process of the one frame of encoded image data after the image header of the corresponding frame. Start from before the image data, stop after the image header of the next frame, stop before the image data of the next frame, and based on the result of the decoding process of the image header of the next frame, the plurality of frame memories, The display image data storage frame memory, the decoded image data storage frame memory, and the reference image data storage frame memory so that a display image data storage frame memory, a decoded image data storage frame memory, and a reference image data storage frame memory exist simultaneously. To switch to one of <br/> A featured MPEG image display control device. 5. The MPEG image display control apparatus according to claim 4, further comprising a distribution circuit that selects a frame memory for storing decoded image data based on a control signal designating a frame memory in which displayed data is stored. . A decoding delay detection unit for detecting that decoding of one frame of encoded image data has not been completed within one frame display period;
A display repeat control unit for controlling repeat display instructions;
6. The MPEG image display according to claim 4, wherein switching of frame memory allocation is masked based on a detection signal from the decoding delay detection unit or a repeat display instruction signal from the display repeat control unit. Control device.

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