KR100653834B1 - Apparatus and Method for controlling graphic ram of display driver IC - Google Patents

Abstract

The present invention relates to an apparatus and method for controlling a graphic RAM in a display driver IC which sets a flag so that a write signal and a scan signal, which are asynchronously generated graphics RAM control signals, do not collide with each other so that an image to be displayed is not lost. An X address generator for generating an X address PRE_X_ADDR [8: 0]; A first signal generator configured to output a first write enable signal PRE_WEN and a scan enable off signal SEN_OFF; A scan address generation unit generating a scan address PRE_S_ADDR [8: 0] and a cell scan address SEL_SADDR; The first scan enable signal PRE_SEN1 and the second scan enable in response to the scan enable off signal SEN_OFF input from the first signal generator and the line clock CK and oscillator clock OSCCK input from the outside. A second signal generator generating a signal PRE_SEN2; A flag generator which generates a second flag signal POST_FLAG in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside; A second flag signal POST_FLAG input from the flag generator, an X address PRE_X_ADDR [8: 0] input from the X address generator, and a first write enable signal input from the first signal generator; PRE_WEN), a scan address PRE_S_ADDR and a cell scan address SEL_SADDR input from the scan address generation unit, a first scan enable signal PRE_SEN1 and a second scan enable signal input from the second signal generation unit A muxing unit configured to mux PRE_SEN2 to output an X address X_ADDR [8: 0], a scan enable signal INT_SEN, and a second write enable signal WEN; and a third scan enable output from the muxing unit And a third signal generator configured to generate a fourth scan enable signal SEN in response to the signal INT_SEN.

Display Driver Icy, Graphics RAM, Flags

Description

Apparatus and Method for controlling graphic ram of display driver IC}

1 is a block diagram for explaining a configuration of a graphic SRAM having a conventional six transistor structure;

2 is a diagram for explaining a data recording method which is usually performed in the graphics RAM;

3 is a block diagram for explaining a configuration of a graphics RAM control signal generating means in a display driver IC according to the present invention;

4 is a timing diagram illustrating a method of generating a first signal PRE_SEN;

FIG. 5 is a timing diagram for describing a control method of a second signal POST_FLAG. FIG.

6 is a timing diagram for explaining a method for selecting a third signal (SRAM Scan);

7 is a timing diagram illustrating a method of generating a graphics RAM control signal using a DE signal when using an RGB interface;

8 is an operation timing diagram at the time of RGB interface.

*** Explanation of symbols on main parts of drawing ***

10: X address generator 20: First signal generator

30: scan address generator 40: second signal generator

50: muxing section 60: third signal generating section

70: flag generator

The present invention relates to an apparatus and method for controlling graphics RAM in a display driver IC.

In particular, the present invention relates to an apparatus and method for controlling a graphic RAM in a display driver IC in which a write signal and a scan signal, which are graphics RAM control signals asynchronously generated by setting a flag, do not collide with each other so that an image to be displayed is not lost.

General graphics memory has a scan function in addition to the write / read function. The scan function does not output data stored in the graphics memory to the outside of the graphics memory through the I / O bus, but simultaneously outputs as many buses as one line of the panel.

That is, as shown in FIG. 1, a graphic SRAM having a six transistor structure includes a row decoder / wordline buffer 100, a data input / output selection unit 110, a data input / output unit 120, and scan data output. The unit 130 is composed.

The row decoder / wordline buffer 100 decodes a row address input from an address counter (see FIG. 2) to generate m word line selection signals, or decodes a scan address input from the address counter to m Word line select signals WL1 to WLm are generated.

The data input / output selector 110 selects a predetermined bit line pair from among n bit line pairs (((BL1, BL1B) to (BLn, BLnB)) in response to a page selection signal input from a controller (not shown). Allow data to be input or output.

The data input / output unit 120 inputs data to the data input / output selection unit 110 in response to the write enable signal input from the controller, and the data input / output selection unit 110 in response to the read enable signal input from the controller. Outputs data from

The scan data output unit 130 outputs data output from the n bit lines BL1 to BLn as scan data Sout in response to the scan enable signal input from the controller.

In the graphic SRAM having the six-transistor structure configured and operated as described above, the bit line pairs BIT and BITB and the row decoder / word line buffer 100 open the word line every time the write function is performed together with the scan function. It is set. In other words, since the word line is set to be opened in units of rows, the same operation as accessing the remaining row parts is performed in addition to the part to be accessed each time a write function is performed.

This will be described in more detail with reference to FIG. 2. When writing data to the graphics RAM, one address is allocated to the data. Therefore, an address allocated to write data to RAM is set, one data is output to RAM, and then a write enable signal is output to write one data to one storage cell. That is, in order to write n rows of data one line, n addresses must be set, and n write enable signals must be output to RAM to write one line.

The present invention has been made in response to the above requirements, and an object of the present invention is to set a flag so that a write signal and a scan signal, which are asynchronously generated graphics RAM control signals, do not collide with each other so that an image to be displayed is not lost. The present invention provides a graphic RAM controller and method in a display driver IC.

One embodiment of the present invention proposed to solve the above technical problem, in the display driver Isis, an X address generation unit for generating an X address (PRE_X_ADDR [8: 0]); A first signal generator configured to output a first write enable signal PRE_WEN and a scan enable off signal SEN_OFF; A scan address generation unit generating a scan address PRE_S_ADDR [8: 0] and a cell scan address SEL_SADDR; The first scan enable signal PRE_SEN1 and the second scan enable in response to the scan enable off signal SEN_OFF input from the first signal generator and the line clock CK and oscillator clock OSCCK input from the outside. A second signal generator generating a signal PRE_SEN2; A flag generator which generates a second flag signal POST_FLAG in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside; A second flag signal POST_FLAG input from the flag generator, an X address PRE_X_ADDR [8: 0] input from the X address generator, and a first write enable signal input from the first signal generator; PRE_WEN), a scan address PRE_S_ADDR and a cell scan address SEL_SADDR input from the scan address generation unit, a first scan enable signal PRE_SEN1 and a second scan enable signal input from the second signal generation unit A muxing unit configured to mux PRE_SEN2 to output an X address X_ADDR [8: 0], a scan enable signal INT_SEN, and a second write enable signal WEN; and a third scan enable output from the muxing unit And a third signal generator configured to generate a fourth scan enable signal SEN in response to the signal INT_SEN.

Hereinafter, a method of controlling a graphic RAM in a display driver IC will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the present invention is applied to a display driver IC including an X address generator 10 for generating an X address PRE_X_ADDR [8: 0], a first write enable signal PRE_WEN, A first signal generator 20 for outputting a scan enable off signal SEN_OFF, a scan address generator 30 for generating a scan address PRE_S_ADDR [8: 0] and a cell scan address SEL_SADDR; The first scan enable signal PRE_SEN1 and the second in response to the scan enable off signal SEN_OFF input from the first signal generator 20 and the line clock CK and oscillator clock OSCCK input from the outside. The second signal generator 40 which generates the scan enable signal PRE_SEN2, and the second signal generator 40 are configured in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside. Flag generator for generating the 2 flag signal POST_FLAG ( 70, a second flag signal POST_FLAG input from the flag generator 70, an X address PRE_X_ADDR [8: 0] input from the X address generator 10, and the first signal generator From the first write enable signal PRE_WEN input from 20, the scan address PRE_S_ADDR and the cell scan address SEL_SADDR input from the scan address generation unit 30, and the second signal generation unit 40. The first scan enable signal PRE_SEN1 and the second scan enable signal PRE_SEN2 are muxed to receive an X address X_ADDR [8: 0], a scan enable signal INT_SEN, and a second write enable signal WEN. ) And a third signal generator 60 generating a fourth scan enable signal SEN in response to the third scan enable signal INT_SEN output from the muxing unit 50. It is composed of

The second signal generator 40 generates the first and second scan enable signals PRE_SEN1 and PRE_SEN2 by counting the oscillator clock OSCCK at the negative edge of the line clock CK.

The flag generator 70 switches the first flag PRE_FLAG to an active state when data writing is started, generates an address and flag ADDR_END_FLAG when writing to RAM is completed, and then sets the first flag PRE_FLAG1. Write data to graphics RAM by turning it into inactive state.

The third signal generator 60 outputs the first scan enable signal PRE_SEN1 as a final scan enable signal SEN when a write operation and a scan operation occur at the same time, and a second when the scan operation occurs only. The scan enable signal PRE_SEN2 is output as the final scan enable signal SEN.

The flag generator 70 generates a second flag signal POST_FLAG using the data enable signal DE in an RGB interface mode in which image data is displayed on a display panel, and generates the generated second flag signal POST_FLAG. ) Is output to the muxing unit 50.

Referring to the operation of the driver is configured as described above is as follows.

3 to 7, first, the X address generator 100 generates an X address PRE_X_ADDR [8: 0] and outputs it to the muxing unit 50.

The first signal generator 20 outputs the first write enable signal PRE_WEN and the scan enable off signal SEN_OFF, and the scan address generator 30 outputs the scan address PRE_S_ADDR [8: 0]. ) And the cell scan address SEL_SADDR are generated and output to the muxing unit 50.

The second signal generator 40 is configured in response to the scan enable off signal SEN_OFF input from the first signal generator 20 and a line clock CK and an oscillator clock OSCCK input from the outside. The first scan enable signal PRE_SEN1 and the second scan enable signal PRE_SEN2 are generated and output to the muxing unit 50. That is, the second signal generator 40 may generate the first scan enable signal PRE_SEN1 using the line clock CK and the oscillator clock OSC_CK, as shown in the timing diagram of FIG. 4. And the second scan enable signal PRE_SEN2 is blocked by the scan enable off signal SEN_OFF indicating that the RAM write is being performed.

The second signal generator 40 counts the oscillator clock OSC_CK at the negative edge of the line clock CK to generate a first scan enable signal PRE_SEN1 based on the oscillator clock. The scan enable signal PRE_SEN1 is used as the data write timing blocking signal to generate the second scan enable signal PRE_SEN2 by avoiding the data write timing.

The flag generator 70 generates a second flag signal POST_FLAG in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside. In this case, the first flag PRE_FLAG is set to write data to RAM, and the write flag and the scan operation are distinguished using the first flag PRE_FLAG. That is, as shown in FIG. 5, the flag generator 70 makes the second flag POST_FLAG active when data is written to the RAM, and sets the address and flag ADDR_END_FLAG when data is written to the RAM. To make the second flag POST_FLAG inactive. When data is written to RAM again, the operation of making the second flag POST_FLAG active is repeated.

As shown in FIG. 6, the first scan enable signal PRE_SEN1 is output as a fourth scan enable signal SEN in a section in which write and scan operations can occur simultaneously, and in a section in which only a scan occurs. The second scan enable signal PRE_SEN2 is output as the fourth scan enable signal SEN.

The muxing unit 50 generates the second flag signal POST_FLAG input from the flag generator 70, the X address PRE_X_ADDR [8: 0] input from the X address generator 10, and the first signal generation. The first write enable signal PRE_WEN input from the unit 20, the scan address PRE_S_ADDR and the cell scan address SEL_SADDR input from the scan address generator 30, and the second signal generator 40. The first scan enable signal PRE_SEN1 and the second scan enable signal PRE_SEN2 are muxed so that the X address X_ADDR [8: 0], the scan enable signal INT_SEN, and the second write enable signal WEN. )

The third signal generator 60 generates the fourth scan enable signal SEN in response to the third scan enable signal INT_SEN output from the muxing unit 50. That is, as described above, the first scan enable signal PRE_SEN1 is output as the third scan enable signal INT_SEN in a section in which writing and scanning are simultaneously performed, and the second scan enable signal in a section in which only a scan occurs. PRE_SEN2 is output as the third scan enable signal INT_SEN to finally generate the fourth scan enable signal SEN.

Meanwhile, as shown in FIG. 7, a second flag signal POST_FLAG is generated using the data enable signal DE in an RGB interface mode for displaying image data on a display panel, and the generated second flag is generated. The signal POST_FLAG is output to the muxing unit 50. Since the process is the same as described above, a detailed description thereof will be omitted.

That is, as shown in FIG. 8, in the RGB interface, data is updated in the RAM by signals DOTCLK, ENABLE, and DB17-0 input from the outside (controller). The dot clock DOTCLK is an input clock of data, and the enable signal ENABLE is a clock that sets a valid range of data.

Therefore, in the chip, data is written to the RAM in a section in which the enable is low by using an enable signal (ENABLE) input from the outside without creating a separate time while the data is being written to the RAM. You can send a flag.

As described above, the first flag PRE_FLAG and the second flag POST_FLAG are generated by the enable signal ENABLE and operate in the same manner as described above.

The present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention included in the appended claims.

The present invention having the above-described configuration, operation, and preferred embodiments has an effect of preventing a loss of an image to be displayed by setting a flag so that a write signal and a scan signal, which are asynchronously generated graphics RAM control signals, do not collide. .

Claims (10)

An X address generator for generating an X address PRE_X_ADDR [8: 0]; A first signal generator configured to output a first write enable signal PRE_WEN and a scan enable off signal SEN_OFF; A scan address generation unit generating a scan address PRE_S_ADDR [8: 0] and a cell scan address SEL_SADDR; The first scan enable signal PRE_SEN1 and the second scan enable in response to the scan enable off signal SEN_OFF input from the first signal generator and the line clock CK and oscillator clock OSCCK input from the outside. A second signal generator generating a signal PRE_SEN2; A flag generator which generates a second flag signal POST_FLAG in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside; A second flag signal POST_FLAG input from the flag generator, an X address PRE_X_ADDR [8: 0] input from the X address generator, and a first write enable signal input from the first signal generator; PRE_WEN), a scan address PRE_S_ADDR and a cell scan address SEL_SADDR input from the scan address generation unit, a first scan enable signal PRE_SEN1 and a second scan enable signal input from the second signal generation unit A muxing unit which muxes PRE_SEN2 and outputs an X address X_ADDR [8: 0], a scan enable signal INT_SEN, and a second write enable signal WEN; and A third signal generator configured to generate a fourth scan enable signal SEN in response to a third scan enable signal INT_SEN output from the muxing unit; Graphic RAM control device of the display driver IC, characterized in that comprises a. The method of claim 1, wherein the second signal generator, The oscillator clock OSC_CK is counted at the negative edge of the line clock CK to generate a first scan enable signal PRE_SEN1, and the data is generated using the first scan enable signal PRE_SEN1 as a data write timing blocking signal. And a second scan enable signal (PRE_SEN2) is generated avoiding the write timing. The method of claim 1, wherein the flag generator, When writing data is started, the first flag PRE_FLAG is changed to the active state. When writing to the RAM is completed, the address and flag ADDR_END_FLAG is generated, and the first flag PRE_FLAG1 is switched to the inactive state. A graphic RAM controller of a display driver IC, which writes data to a RAM. The method of claim 1, wherein the second signal generator, The first scan enable signal PRE_SEN1 is output as the final scan enable signal SEN in a section in which a write operation and a scan operation occur simultaneously, and the second scan enable signal PRE_SEN2 is output in a section in which only a scan operation occurs. A graphic RAM controller of a display driver IC, characterized by outputting a final scan enable signal (SEN). The method of claim 1, wherein the flag generator, In the RGB interface mode for displaying image data on a display panel, a second flag signal POST_FLAG is generated using the data enable signal DE, and the second flag signal POST_FLAG is output to the muxing unit. Graphic RAM controller of display driver IC. In the graphic RAM control method of the display driver IC, (1) generating an X address PRE_X_ADDR [8: 0]; (2) outputting a first write enable signal PRE_WEN and a scan enable off signal SEN_OFF; (3) generating a scan address PRE_S_ADDR [8: 0] and a cell scan address SEL_SADDR; (4) The first scan enable signal PRE_SEN1 and the second scan in response to the scan enable off signal SEN_OFF input from the first signal generator and the line clock CK and oscillator clock OSCCK input from the outside. Generating an enable signal PRE_SEN2; (5) generating a second flag signal POST_FLAG in response to an address and flag ADDR_END_FLAG, a first flag PRE_FLAG, and a first write enable signal PRE_WEN input from the outside; (6) The second flag signal POST_FLAG input from the flag generator, the X address PRE_X_ADDR [8: 0] input from the X address generator, and the first write enable signal input from the first signal generator ( PRE_WEN), the scan address PRE_S_ADDR and the cell scan address SEL_SADDR input from the scan address generation unit, the first scan enable signal PRE_SEN1 and the second scan enable signal PRE_SEN2 input from the second signal generation unit. Muxing to output an X address X_ADDR [8: 0], a scan enable signal INT_SEN, and a second write enable signal WEN; and (7) generating a fourth scan enable signal SEN in response to the third scan enable signal INT_SEN output from the muxing unit; Graphic RAM control method of the display driver IC, characterized in that consisting of. According to claim 6, wherein the (4) process, The oscillator clock OSC_CK is counted at the negative edge of the line clock CK to generate a first scan enable signal PRE_SEN1, and the data is generated using the first scan enable signal PRE_SEN1 as a data write timing blocking signal. And a second scan enable signal PRE_SEN2 is generated by avoiding write timing. The method of claim 6, When writing data is started, the first flag PRE_FLAG is changed to the active state. When writing to the RAM is completed, the address and flag ADDR_END_FLAG is generated, and the first flag PRE_FLAG1 is switched to the inactive state. A method of controlling a graphic RAM of a display driver IC, comprising writing data to a RAM. The method of claim 6, The first scan enable signal PRE_SEN1 is output as the final scan enable signal SEN in a section in which a write operation and a scan operation occur simultaneously, and the second scan enable signal PRE_SEN2 is output in a section in which only a scan operation occurs. A method of controlling a graphic RAM of a display driver IC, which outputs the final scan enable signal SEN. The method of claim 6, The second flag signal POST_FLAG is generated by using the data enable signal DE in the RGB interface mode for displaying image data on the display panel, and the generated second flag signal POST_FLAG is output to the muxing unit. Graphic RAM control method of display driver IC.

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