KR20050055281A - Graphic memory having a high speed writing and the method thereof - Google Patents

Abstract

According to the present invention, the write function can be performed irrespective of the scan function, and n-1 times are indirectly written to the latch and n-1 should be written in n-page units instead of 1-pages. The present invention relates to a graphics memory having a fast write function for operating a word line at the nth write time so that data written to a latch is collectively written to a ram core, and a fast write method thereof. A data input / output unit configured to output predetermined data in response to an input write enable signal; A page decoder to operate a corresponding page module in response to a page address input from an external device, and to output data input from the data input / output unit through the page module; A fast write interface unit configured to store data input through the page module in response to a fast mode enable signal input from an external device, and output the stored data to a RAM in response to a fast write enable signal input from an external device; And a row address buffer for outputting the high speed mode enable signal, the fast write enable signal, the row address, and the write enable from the outside to the data input / output unit, the page decoder, and the fast write interface unit to be written line by line to the RAM core. And a timing controller.

Description

Graphic memory having a high speed writing and the method

The present invention relates to a graphics memory having a fast write function and a fast write method thereof.

More specifically, the write function can be performed irrespective of the scan function, and the n-th one is indirectly written to the latch by writing n-times by n-page units instead of 1-pages. The present invention relates to a graphics memory having a fast write function for operating word lines so that data written in a latch is collectively written to a ram core when an nth write is performed.

General graphics memory has a scan function in addition to the write / read function. The scan function does not output data stored in the graphics memory to the outside of the graphics memory through the I / O bus, but simultaneously outputs as many buses as one line of the panel.

That is, as shown in FIG. 1, a graphic SRAM having a six transistor structure includes a row decoder / wordline buffer 100, a data input / output selection unit 110, a data input / output unit 120, and scan data output. The unit 130 is composed.

The row decoder / wordline buffer 100 decodes a row address input from an address counter (see FIG. 2) to generate m word line selection signals, or decodes a scan address input from the address counter to m Word line select signals WL1 to WLm are generated.

The data input / output selector 110 selects data from a predetermined bit line pair among n bit line pairs (BL1, BL1B) to (BLn, BLnB) in response to a page selection signal input from a controller (not shown). To be input or output.

The data input / output unit 120 inputs data to the data input / output selector 110 in response to a write enable signal input from the controller, and responds to the read enable signal input from the controller. Outputs data from

The scan data output unit 130 outputs data output from the n bit lines BL1 to BLn as scan data Sout in response to the scan enable signal input from the controller.

In the graphic SRAM having the six-transistor structure configured and operated as described above, the bit line pairs BIT and BITB and the row decoder / word line buffer 100 open the word line every time the write function is performed together with the scan function. It is set. That is, since the word line is set to be opened in units of rows, the same operation as accessing the remaining row parts is performed in addition to the part to be accessed each time the write function is performed.

This will be described in more detail with reference to FIG. 2. When writing data to the graphics RAM, one address is assigned to the data. Therefore, an address allocated to write data to RAM is set, one data is output to RAM, and then a write enable signal is output to write one data into one storage cell. In other words, to write n rows of data, n addresses must be set and n write enable signals must be output to RAM to write one row.

Therefore, there is a problem that unnecessary current is consumed when performing the write function.

Therefore, the present invention has been made to solve the problems according to the prior art as described above, the object of the present invention is to perform the write function irrespective of the scan function, and in units of n-page rather than 1-page N-1 writes indirectly to the latch, n-1 writes indirectly to the latch, and the wordline is activated at the last nth write so that the data written to the latch is written to the ram core in a batch. The present invention provides a graphics memory and a fast write method having a fast write function to minimize the current consumption by dramatically reducing the frequency of operation.

It is also an object of the present invention to provide a graphics memory having a fast write function and a fast write method thereof so as to reduce the number of accesses to the ram cells and significantly reduce the limitation of the write function due to the scan function.

One embodiment of the present invention for achieving the above object, in the graphic SRAM, a data input / output unit for outputting predetermined data in response to a write enable signal input from the outside; A page decoder to operate a corresponding page module in response to a page address input from an external device, and to output data input from the data input / output unit through the page module; A fast write interface unit configured to store data input through the page module in response to a fast mode enable signal input from an external device, and output the stored data to a RAM in response to a fast write enable signal input from an external device; And a row address buffer for outputting the high speed mode enable signal, the fast write enable signal, the row address, and the write enable from the outside to the data input / output unit, the page decoder, and the fast write interface unit to be written line by line to the RAM core. And a timing controller.

In addition, the present invention provides a row decoder / wordline buffer for outputting scan data through a scan data output unit in response to a scan enable signal input from the row address buffer / timing controller while the fast write interface unit is performing a write operation. Characterized in that configured to include.

The fast write interface unit may include a page mux unit configured to output data recorded in a RAM core; A data latch unit selected by a selection signal input from the page decoder and driven in response to the fast mode enable signal to receive data output through the page mux unit; A first gate circuit configured to receive a reverse phase and a high speed mode enable signal of the page signal selected from the page mux unit through a latch and output a high level signal to an output terminal; A second gate circuit configured to receive an output signal of the first gate circuit and a mux enable signal, and output a high level signal to an output terminal when both signals are high level signals; And a mux for recognizing the high level signal of the second gate circuit as a write enable signal and collectively outputting data currently stored in the data latch unit to the RAM core.

In addition, another embodiment of the present invention, a data input and output unit for outputting predetermined data in response to a write enable signal input from the outside; A page decoder to operate a corresponding page module in response to a page address input from an external device, and to output data input from the data input / output unit through the page module; A fast write interface unit configured to store data input through the page module in response to a fast mode enable signal input from an external device, and output the stored data to a RAM in response to a fast write enable signal input from an external device; And a row address buffer for outputting the high speed mode enable signal, the fast write enable signal, the row address, and the write enable from the outside to the data input / output unit, the page decoder, and the fast write interface unit to be written line by line to the RAM core. In the high-speed write recording method of a graphic SRAM having a timing / timing control unit, a data written to a RAM core is sequentially input from a data input / output unit in response to a high-speed mode enable signal, and the high-speed write enable when the last data is input. Responding to the signal when the last data is stored in the RAM core, characterized in that it comprises a step of storing the pre-input data in the ram core collectively.

In addition, the present invention includes the step of outputting the scan data through the scan data output unit in response to the scan enable signal input from the row address buffer / timing controller while the fast write interface unit is performing a write operation. It features.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a schematic block diagram illustrating a configuration of a graphic memory having a fast write function according to the present invention, FIG. 4 is a diagram for explaining a configuration of a fast write interface unit applied to FIG. 3, and FIG. FIG. 6 is a diagram illustrating a data writing method in a graphics RAM having a fast write function according to FIG. 6. FIG. 6 is a diagram illustrating a case where the present invention is applied to a multi-chip.

As shown in FIG. 3, a data input / output unit 240 for outputting predetermined data in response to a write enable signal input from the low address buffer / timing controller 210, and a low address buffer / timing controller 210. A page decoder (250) for allowing a corresponding page module (not shown in the drawing) to be operated in response to a page address inputted from the page, and outputting data input from the data input / output unit 240 through the page module. Data stored through the page module in response to the fast mode enable signal input from the buffer / timing controller 210 and stored in response to the fast write enable signal input from the low address buffer / timing controller 210. And the high speed light interface unit 260 for outputting the data to the RAM, and the like. A high speed mode enable signal, a fast write enable signal, a row address, and a write enable signal are inputted to the data input / output unit 240, the page decoder 250, and the fast write interface unit 260. A row address buffer / timing control unit 210 for writing in line units 200 and a scan input from the row address buffer / timing control unit 210 while the fast write interface unit 250 is performing a write operation. The row decoder / wordline buffer 220 is configured to output scan data through the scan data output unit 270 in response to the enable signal.

As shown in FIG. 4, the fast write interface unit 260 includes a page mux unit 261 for outputting data recorded in the RAM core 200 and a selection input from the page decoder 250. A data latch unit 265 selected by a signal and driven in response to the fast mode enable signal to receive data output through the page mux unit 261 and the page mux unit through a latch 262. A first gate circuit 263 for receiving a reverse phase and a high speed mode enable signal of the page signal selected from the 261 and outputting a high level signal to an output terminal, and an output signal and a mux in of the first gate circuit 263; A second gate circuit 264 and a high level of the second gate circuit 264 for receiving the enable signal and outputting a high level signal to an output terminal when both signals are high level signals; The mux 266 is configured to recognize the bell signal as a write enable signal and output the data stored in the data latch unit 265 to the RAM core 200 in a batch. Here, the mux enable signal input to the second gate circuit unit 264 is at a high level, and when there is data output from the data input / output unit 240, the signal output to the output terminal of the second gate circuit unit 264 is It depends on the signal level input from the first gate circuit portion 263.

Reference numeral 230 denotes a dependency timing controller.

The operation of the graphics RAM having the fast light processing function configured as described above is as follows.

First, the row address buffer / time controller 210 may input a high speed mode enable signal, a fast write enable signal, a row address, and a write enable from the data input / output unit 240, the page decoder 250, and the high speed. The data output through the data interface 260 is written to the RAM core 200 in a line unit.

That is, the data input / output unit 240 outputs predetermined data to the fast write interface unit 260 in response to the write enable signal input from the low address buffer / timing controller 210. Meanwhile, the page decoder 250 causes the corresponding page module to operate in response to the page address input from the low address buffer / timing controller 210, and outputs data input from the data input / output unit 240 through the page module. Be sure to

In addition, the fast write interface unit 260 stores data input through the page module in response to the fast mode enable signal input from the low address buffer / timing controller 210, and the low address buffer / timing controller 210. The stored data is output to the RAM in response to the fast write enable signal input from the RAM. That is, as shown in FIG. 5, all data of one line is stored in the latch, and when the last data is received, the data received together with the write signal is stored in the latch together with the last data. The data is collectively recorded in the core 200 (graphic RAM).

On the other hand, the detailed operation of the fast write interface unit 260, as shown in Figure 4, the data latch unit 265 is selected by the selection signal input from the page decoder 250, the high speed mode It starts to operate in response to the enable signal and maintains a standby state for receiving data. The page mux unit 261 outputs data to be written to the RAM core 200 in response to a write enable signal input through the row address buffer / timing controller 210. In this case, the high speed mode enable signal is output to the second gate circuit unit 264 via the first gate circuit unit 263. In this case, since the mux disable signal is input to the second gate circuit unit 264, the mux disable signal is input to the mux unit 266. Accordingly, the mux unit 266 maintains the disabled state.

The data passing through the page mux part 261 is input to the data latch part 265, and is input to the mux part 266 through the data latch part 265. At this time, since the mux enable signal is not input to the mux unit 266, the mux unit 266 maintains the disabled state.

Meanwhile, when the last data is output, the mux enable signal is input to one terminal of the second gate circuit unit 264, and the mux enable signal is output to the mux unit 266 through the output terminal of the second gate circuit unit 264. do.

In response to the mux enable signal, the mux unit 266 outputs and stores the data stored in the data latch unit 265 together with the last data input to the ram core 200.

Meanwhile, the row address buffer / timing control unit 210 performs a scan function because the word line is used while the mux unit 266 performs a process of collectively outputting and writing data to the ram core 200 as described above. Do not use at the same time. That is, the decoder / wordline buffer 220 is input from the row address buffer / timing control unit 210 only while the fast write interface unit 250 writes up to n-1 data which is the data immediately before the last data. In response to the scan enable signal, scan data is output through the scan data output unit 270.

6 is a diagram illustrating a multi-chip in which the fast write processing function of the present invention is applied, and the word line may be operated by selecting only chips written for each RAM chip. That is, if data is recorded at high speed from the middle of the second chip (CHIP2) to the middle of the fourth chip (CHIP4), the data from 0 to (n-1) is written while writing the nth data to the fourth chip (CHIP4). The word line is opened to write data written to the latch to the memory core. Of course, at this time, not all chips are operated, but only the second to fourth chips of which data is written.

Accordingly, the present invention enables the write function to be performed irrespective of the scan function, and writes n-1 times to the latch indirectly by writing n times to be written in units of n pages rather than 1 pages. When the last nth write is performed, the word line is operated so that the data written in the latch is collectively written to the ram core, thereby dramatically reducing the frequency of operation of the word line and minimizing the current consumption.

In addition, in the present invention, n-1 times are indirectly written to the latch to write n times when the write function is performed, and the word line is operated by applying the batch write method when the last write operation, thereby accessing the RAM CELL. The number of times can be reduced, which has the effect of reducing the write function due to the scan function.

The present invention is not limited only to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

1 is a block diagram for explaining a configuration of a graphic SRAM having a conventional six transistor structure;

2 is a diagram for explaining a data recording method which is usually performed in the graphics RAM;

3 is a schematic block diagram illustrating a configuration of a graphics memory having a fast write function according to the present invention;

4 is a view for explaining the configuration of the high-speed light interface unit applied to FIG.

5 is a view for explaining a data writing method in a graphics RAM having a fast write function according to the present invention;

6 is a diagram for explaining a case where the present invention is applied to a multi-chip.

*** Explanation of main parts of drawing ***

200: ram core

210: low address buffer / timing control unit

220: Low Decoder / Wordline Buffer

230: dependent timing control unit

240: data input and output unit

250: page decoder

260: high speed light interface unit

270: scan data output unit

Claims (5)

In graphics SRAM, A data input / output unit configured to output predetermined data in response to a write enable signal input from the outside; A page decoder to operate a corresponding page module in response to a page address input from an external device, and to output data input from the data input / output unit through the page module; A fast write interface unit configured to store data input through the page module in response to a fast mode enable signal input from an external device, and output the stored data to a RAM in response to a fast write enable signal input from an external device; And A row address buffer for outputting the high speed mode enable signal, the fast write enable signal, the row address, and the write enable from the outside to the data input / output unit, the page decoder, and the fast write interface unit to be written line by line to the RAM core. A timing controller; Graphics memory having a fast write function, characterized in that consisting of. The method of claim 1, And a row decoder / wordline buffer configured to output scan data through a scan data output unit in response to a scan enable signal input from the row address buffer / timing controller while the fast write interface unit is performing a write operation. A graphics memory having a fast write function. The method of claim 1, wherein the high speed light interface unit, A page mux for outputting data recorded in the RAM core; A data latch unit selected by a selection signal input from the page decoder and driven in response to the fast mode enable signal to receive data output through the page mux unit; A first gate circuit configured to receive a reverse phase and a high speed mode enable signal of the selected page signal through the latch and output a high level signal to an output terminal; A second gate circuit configured to receive an output signal of the first gate circuit and a mux enable signal, and output a high level signal to an output terminal when both signals are high level signals; And A mux for recognizing the high level signal of the second gate circuit as a write enable signal and collectively outputting data currently stored in the data latch unit to a RAM core; Graphics memory having a fast write function, characterized in that consisting of. A data input / output unit configured to output predetermined data in response to a write enable signal input from the outside; A page decoder to operate a corresponding page module in response to a page address input from an external device, and to output data input from the data input / output unit through the page module; A fast write interface unit configured to store data input through the page module in response to a fast mode enable signal input from an external device, and output the stored data to a RAM in response to a fast write enable signal input from an external device; And A row address buffer for outputting the high speed mode enable signal, the fast write enable signal, the row address, and the write enable from the outside to the data input / output unit, the page decoder, and the fast write interface unit to be written line by line to the RAM core. In the fast write method of a graphic SRAM having a timing controller, When the data recorded in the RAM core is sequentially input from the data input / output unit in response to the high speed mode enable signal, and the last data is stored in the RAM core in response to the fast write enable signal when the last data is input, the input is performed in advance. And writing the stored data in a RAM core in a batch. The method of claim 4, wherein And outputting scan data through a scan data output unit in response to a scan enable signal input from the row address buffer / timing control unit while the fast write interface unit is performing a write operation. Fast write recording method.