JPS60254225A - Access method of video ram - Google Patents

Abstract

PURPOSE:To switch a display screen at a high speed by deciding a CPU priority mode when accesses are given to a video RAM from both a CPU and a display controller. CONSTITUTION:A video RAM2 receives accesses from both a CPU1 and a display controller 3 for write/read operations. In this case, the CPU1 itself is made wait for a prescribed period of time every time a 1-byte access is given from the CPU1. A timing controller 7 performs an access through the side of the CPU1. Then a chip selection signal CS is delivered from the CPU1 for selection of the video RAM2. The signal CS is supplied to the controller 7 together with a writing signal WR, etc. for production of a wait signal WAIT. The controller 3 is disabled after a prescribed period of time elapses. While a gate 6 is opened to perform the write/read operations to the video RAM2 from the CPU1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to a video RA that speeds up access to video RAM provided in motherboards, display terminals, etc.
Regarding the access method of M.

In general, display contents corresponding to the display no. Display on the display screen. In this way, both the CPU and the display controller mutually access one video style, but in this case, in the prior art, as will be described later, generally the display side is given priority access to the video style. On the other hand, the CPU side can only access it during free time. In particular, when using a liquid crystal display, the ratio of video RAM usage by the CPU and display controller is, for example, 1:10.
As a result, the CPU access time becomes shorter, and switching the display screen, especially when rewriting the entire screen, takes time, and the desired switching speed cannot be achieved.

[Conventional technology]

FIG. 4 shows the interrelationship between the video RAM, the CPU, and the display controller when the conventional video RAM access method is applied; 1 indicates the CPU 12;
3 indicates a video-RAM, and 3 indicates a display controller. In this case, while the display controller 3 side is constantly using the video RAM, the signal output from the BUSY terminal of the display controller 3 causes
First, the multiplexers 41 and 42 connect the address bus and data bus on the display controller side to the video RAM, and further control darts 5 and 6 using these signals, and a WAIT signal from gate 5 that makes CPTJ 1 standby. is output, and the gate 6 is closed to prevent read or write signals from the CPU 1 from being input to the video RAM.

During the so-called idle time when the display controller 3 side does not use the video RAM, there is no signal output from the BUSY terminal, so that the multiplexer 41.
42 connects the address bus and data bus connected to the video RAM from each path on the display controller side to the CPU.
At the same time, the wait signal output from the gate 5 is stopped and the dart 6 is opened to write data from the CPU to the video section M or from the video RAM to the CP.
Enables data reading to U. Note that 1) indicates a read signal, WR indicates a write signal, and C8 indicates an upper address, that is, a chip select signal for selecting a specific video RAM.

[Problem that the invention seeks to solve]

In this way, the display controller has priority in accessing the video RAM, and the CPU can only access it during free time when the display controller is not accessing the video RAM. I can only reach it. For this reason, the rewriting speed becomes slow when the screen is continuously rewritten, such as when scrolling up. In particular, when the display controller is used in graphic mode, the CPU accesses the video style to fill the screen content with dot images.In this case, one character consists of, for example, 8 bytes of data, so for example In the case of a 2,000-character optical display, the allowable capacity is as much as 16 kilobytes, so if the display screen is a liquid crystal, the CPU will be able to handle the video RA.
Since the ratio of the time during which M can be accessed is only about 10 times, there is a problem in that the switching speed when the entire screen is rewritten is significantly reduced.

The present invention solves such problems, and its purpose is to increase the ratio of time during which the CPU can access the video RAM, in other words, increase the usage ratio of the video RAM from the CPU side, thereby speeding up the switching of display screens. At the same time, the purpose is to maintain the clarity of the display screen.

[Means for solving problems]

According to the present invention, in order to access the video RAM from both the cpty and the display controller,
A CPU priority mode is set, and a wait signal of a predetermined length of time is supplied to the CPU from a timing controller controlled by the CPU every time a predetermined bit, for example, 1 byte (8 bits) or 1 word (16 bits) is accessed. , a video RAM access method is provided in which access is performed from the CPU side while the display controller is disabled while the wait signal is released.

[For production]

In the video RAM access method described above, each time the CPU accesses a predetermined pit, such as 1 byte or 1 word, to the video RAM, a wait signal of a predetermined length is supplied to the CPU itself, during which time the CPU waits and displays the The display controller is enabled to operate on the controller side, and while the wait signal is canceled, the display controller is disabled, that is, its movement is stopped, and access from the CPU side is performed.

[Example] FIG. 1 shows the mutual relationship between the video RAM, the CPU, and the display controller 2 when the video RAM access method of the present invention is applied, and the parts corresponding to FIG. The same reference numerals as in the figure are given.

In this case, in the prior art shown in FIG. 4, the display controller has priority in accessing the video RAM as described above, and the CPU is configured so that it can only access the video RAM during free time when the display controller is not accessing the video RAM. On the other hand, in the present invention shown in FIG. 1, the premise is that the video R
Priority for access to AM is given to the CPU side, and the CPU
On the U side, the timing of access to the video source is controlled. And in this case C
The PU accesses 1 byte (8 bits) or 1 word (16 bits) in one access cycle.

By setting the CPU priority mode for accessing the video RAM in this way, it is possible to speed up the switching of display screens, but on the other hand, if only the CPU accesses the video RAM continuously, the display controller side The display screen disappears or becomes unclear.

For this reason, in the embodiment shown in FIG. 1, each time one byte or one word is accessed from the CPU side, the CPU itself is first made to wait for a predetermined length of time, and then access from the CPU side is made possible. A timing controller 7 is provided for timing control.

That is, in FIG. 1, when a chip select signal dj- for selecting an upper address, that is, a specific video RAM, is output from the CPU side, and a write signal WR or a read signal 1i for the video RAM is output. ,
The timing controller 7 to which these signals are input generates a wait signal WAIT to the CPU to make the CPU wait.

In this case, the wait time is set to an appropriate time depending on the type of display, both to keep the display screen clear to a certain extent and to speed up the rewriting of the display screen. In one example, when the CPU access time is 1 μB, the wait time is 2 μB.

Next, when the predetermined time set in the timing controller 7 has elapsed, the DISP signal supplied to the display terminal D I S EN of the play controller 23
/- signal (when at H level, access from the display side is enabled; when at L level, access from the aτ side is enabled) is set to L level to turn the display controller 3 into a display controller. At the same time, the signal is also supplied to the multiplexers 41, 42 and dart 6, so that the multiplexers 41, 42 switch the address bus and data bus connected to the video RAM from the display controller side to the CPU'U side. , open the dart 6 to which the chip select signal C8 is input. Furthermore, the wait signal WAIT mentioned above is also canceled, so at this point the video RAM is released from the CPU side.
Writing to or reading from is performed. CK is CP
This is a synchronization clock signal given from U to the timing controller.

FIG. 2 shows an example of a specific circuit of the timing controller 7, and FIG. 3 shows a time chart thereof.

Here, the operation of the timing controller will be explained according to its time chart. First, the clock signal CK
In the T1 cycle, the chip select signal C8 becomes L.
level, a predetermined video RAM is selected, and then the CPU applies the write signal WR or the read signal RD from the CPU to the video RAM, and when either of them becomes L level, these signals are input. Ruand Gate 71. The potential at point A becomes L level via the OR gate 72, and as shown in FIG. 3, the wait signal WAIT on the output side of the OR gate 77
is set to L level to put the CPU on standby.

Further, the potential at point A is input to the B terminal of the one-shot multivibrator 75 through the inverter 73, and the potential at point B, which corresponds to the output terminals of the multivibrator 75, is as follows.
The L level is maintained for a set time by the multivibrator 75, and this time determines the time the CPU waits.In addition, for example, a counter is used in place of this one-shot multivibrator, and the count number is You can also set a predetermined time by

On the other hand, during the time set by the multivibrator, the potential at the 0 point corresponding to the output terminal Q reaches the H level, so the DISP/CPU signal on the output side of the ORDART 78 is used for writing or reading from the CPU to the video tone. Even after a signal is generated and the potential at point A goes to L level, it is maintained at H level, and during that time, access from the display controller side is allowed without setting the display controller to disk space.

When the time set in the multivibrator has elapsed, the potential at point B becomes H level, while the potential at point C becomes L level, so at this point the DISP/CPU signal on the output side of ORDART 78 goes to L level. Therefore, the display controller command to the display controller is valid.

On the other hand, the D flip-flop 76 to which the potential at point B is input to its D terminal has a potential at point D, which corresponds to its output terminal Q, at the falling edge of the clock pulse CK immediately after the potential at point B becomes H level. becomes H level. As a result, the wait signal WAIT on the output side of the geoadder door 7 becomes H level, and the standby command to the CPU is released.

Therefore, the CPU that has been on standby until then can now access the video RAM, and one byte or one word is written or read from the video RAM from the CPU.

Then, at the point when this writing or reading is finished, that is, A
When the potential at the point becomes H level, the DISP/CPU signal returns to H level, the DISP pull command to the display controller is released, and one cycle of access is completed.As described above, one cycle of access to video style is completed. basically ends with 4 cycles of clock signal (chip select in T1 cycle) (generates IC8, generates write or read signal in T2 cycle, and generates C in cycle T3).
However, in the present invention, in order to make the CPU wait for a predetermined time, a predetermined number of wait cycles (11) are inserted between the T3 cycle and the T4 cycle. TW is inserted.

As shown in Fig. 3, if the display controller is actually given the DISK APR command, then DISP/
This is the period during which the CPU signal goes to L level, and this is only one cycle of the clock signal. Therefore, even if the ratio of eight cycles to one access cycle is about 100, the period during which the display side is turned into a disk space and its movement is actually stopped is still shorter than that.

〔Effect of the invention〕

According to the present invention, when accessing the video RAM from both the CPU and the display controller, p, C
By setting the PU priority mode, it is possible to speed up the switching of the display screen, and at the same time, maintain the sharpness of the display screen by supplying a wait signal to the CPU for a predetermined time every time a predetermined bit, for example, 1 byte or 1 word is accessed. can do.

(12)

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the mutual relationship between a video RAM, a CPU, and a display controller when a video style access method as an embodiment of the present invention is applied, and FIG. 1 is a circuit diagram showing a specific example; FIG. 3 is a diagram showing a time chart of the timing controller in FIG. 2; FIG. 4 is a circuit diagram showing a video RAM, CPU, and display when the conventional video RAM access method is applied. FIG. 3 is a block diagram showing the interrelationship with a controller. (Explanation of symbols) ■...CPU12...Video controller, 3...Display controller, 41.42...Multiplexer, 5°6...Dart circuit, 7...Timing controller.

Claims (1)

[Claims] 1. When accessing the video RAM from both the CPU and the display controller, set the CPU priority mode, and for each predetermined pit access, send a wait signal of a predetermined length to the CPU from the timing controller controlled by the CPU. While the wait signal is released, the display controller is disabled! 1. A video RAM access method characterized in that access is performed from the CPU side in a state where the video RAM is enabled.