KR100273268B1 - Read/write controller of flash memory - Google Patents

Abstract

PURPOSE: A flash memory read/write controller is provided to be capable of reducing loading of an MCU and increasing a speed by controlling a flash memory with a hardware. CONSTITUTION: The first register(70) stores an address(Address£15:0|), and the second register(71) stores data(DATA£7:0|). The first OR gate(OR1) receives a chip selection bar signal(/CS) and a write bar signal(/WR), and the second OR gate(OR2) receives the chip selection bar signal(/CS) and a read bar signal(/RD). A flag(73) is set by the data, the address and the write bar signal. A control part(72) receives output signals of the first and second OR gates and a flag signal of the flag(73), and outputs a command signal and control signals for controlling a read/write operation of a flash memory and a sector/chip erase operation in response to the received signals. A multiplexer(74) receives outputs of the first and second registers(70, 71) to perform a multiplexing transfer operation in response to a control signal from the control part(72).

Description

Flash Memory Lead / Write Controller {READ / WRITE CONTROLLER OF FLASH MEMORY}

TECHNICAL FIELD The present invention relates to a flash memory read / write controller, and more particularly, to a flash memory read / write controller, which is used as a peripheral of MCU for easier and faster access.

FIG. 1 is a block diagram showing the configuration of a conventional flash memory read / write controller. As shown in FIG. 1, an address signal Address [15: 0], a chip enable bar signal / CE, and an out enable bar signal / MC oil 10 which controls to read or write predetermined data DATA [7: 0] after sequentially outputting OE); The address signal Address [15: 0], the chip enable bar signal / CE, and the out enable bar signal / OE of the MCU 10 are sequentially input, and accordingly, predetermined data DATA [7: 0]) and a flash memory 11 for reading or writing. The operation of the conventional apparatus configured as described above will be described with reference to the accompanying drawings.

First, when the data DATA [7: 0] is read, the MC oil 10 has an address signal Address [15: 0] as shown in FIG. 4A and a chip enable as shown in FIG. 4B. The bar signal / CE and the out enable bar signal / OE as shown in FIG. 4 (c) are sequentially output, and accordingly, the flash memory 11 stores the data of the address (Address [15: 0]). DATA [7: 0]) is outputted, and the MC oil 10 receives the data DATA [7: 0] output from the flash memory 11 and outputs the data DATA [7: 0]. Program a predetermined program.

On the contrary, when data DATA [7: 0] is written to the flash memory 11, the MCU 10 writes an address (Address [15: 0]) for four cycles as shown in FIG. And data DATA [7: 0], and then it is checked whether data DATA [7: 0] is written to the flash memory 11.

After the MCU 10 writes one byte to the flash memory 11 once, the entire chip is erased because the one byte cannot be written to the same address (Address [15: 0]) again. Or by dividing into sectors.

That is, the flash memory 11 can write to one address (Address [15: 0] only once, and cannot write twice. Therefore, the flash memory 11 cannot write other data DATA [7: 0] to the same address (Address [ 15: 0]), you have to erase sectors or erase chips.

At this time, the chip erase (Chip_Erase) must be operated up to six cycles as shown in Figure 2, and the sector erase (Sector_Erase) must also be performed for six cycles.

After the above-described chip raise (Chip_Erase) and sector erase (Sector_Erase) performs a check operation as shown in the flowchart of FIG.

That is, after erasing the chip or sector, it is checked whether the data DATA [7: 0] is FFH. After the flash memory 11 is written, the data DATA [7: 0] polling operation as shown in FIG. 3 is performed. do.

At this time, the data DATA [7: 0] polling operation of FIG. 3 will be described in detail. After writing, the bit of the data DATA [7] of the flash memory 11 is the data DATA [7: 0]. Compare to the 7th bit of.

Then, it checks whether the bit of data DATA [5] is '1', and if it is '1', finally reads data DATA [7: 0] and compares data DATA [7] again. If it is different, it is regarded as a fail. If the data DATA [5] is not 1, the data is read continuously and the data DATA [7: 0] are compared.

However, while the conventional device operating as described above can use the flash memory in the same manner as the method using the general memory, it cannot read / write like the general memory, and it can be chip erase (Chip_Erase) or sector erase (Sector_Erase). By requiring a lot of time for the MC in the city of the city to give a lot of time burden to the MC, and also had a problem of reducing the performance of the MC.

Accordingly, an object of the present invention is to provide a flash memory read / write controller that can be accessed more easily and at a higher speed by using MC U as a peripheral.

1 is a block diagram showing the configuration of a conventional flash memory read / write controller.

FIG. 2 shows a program cycle in FIG. 1; FIG.

Figure 3 is a flowchart of data polling in Figure 1;

4 is a timing diagram in FIG. 1;

Fig. 5 is a flowchart of a write operation in Fig. 1;

Figure 6 is a flowchart of a data ease operation in Figure 1;

Fig. 7 is a block diagram showing the configuration of the flash memory read / write controller of the present invention.

Figure 8 is a block diagram showing the configuration using the MC U peripheral to implement the Figure 7.

* Description of the symbols for the main parts of the drawings *

70, 71: register 72: control unit

73: flag 74: multiplexer

75: command generator 76: cycle counter

77: flash controller

The above object includes: first and second registers for storing an address Address [15: 0] and data DATA [7: 0]; A first oar gate that receives the chip select bar signal / CS and the light bar signal / WR and performs an operation on the chip select bar signal / CS and the write bar signal / WR; A second orifice that receives the chip select bar signal / CS and the lead bar signal / RD and calculates the result; A flag that receives data DATA [7: 0], an address and a write bar signal, and sets a flag bit accordingly; A control unit which receives the operation signals of the first and second orifices and the flag signals of flags and outputs command signals and control signals for controlling read / write operations and sector / chip laser operations of the flash memory; This is achieved by configuring a multiplexer which receives the signals of the first and second registers and the command signal and transmits them by the control signal of the controller.

Fig. 7 is a block diagram showing an embodiment of the read / write controller of the flash memory of the present invention, which stores an address (Address [15: 0]) and data DATA [7: 0] as shown therein. First and second registers 70 and 71; A first oar gate OR1 that receives the chip select bar signal / CS and the light bar signal / WR and performs an operation on the chip select bar signal / CS and the write bar signal / WR; A second orifice OR2 that receives the chip select bar signal / CS and the lead bar signal / RD and calculates the result; A flag 73 which receives data DATA [7: 0], an address and a write bar signal, and sets a flag bit accordingly; The operation signals of the first and second OA gates OR1 and OR2 and the flag signals of the flag 73 are input to control command / write and read / write operations of the flash memory and sector / chip laser operations. A control unit 72 for outputting a control signal; The multiplexer 74 receives a signal and a command signal of the first and second registers 70 and 71 and multi-transmits it by a control signal of the controller 72.

The controller 72 outputs the write command signal, the chip_erase command signal, and the sector_erase command signal in synchronization with the counting signal of the cycle counter, which will be described later, by the bit value of the flag. Wow; A cycle counter 76 for counting clocks from the first cycle to the sixth cycle; A flash controller 77 which controls the interface of the flash memory 11 by the bit value of the flag 73 is described. The operation of one embodiment of the present invention configured as described above will be described with reference to FIG.

First, an address of one byte that MCU 10 intends to write to the first register 70 in order to write data DATA [7: 0] to the flash memory 11 through the interface of the flash memory 11. Set (Address [15: 0]).

Thereafter, the data DATA [7: 0] to be written is set in the second register 71, and the address Address [15: 0], the data signal DATA [7: 0] and the write bar signal are set. (If the flag is set by / WR_ and EN = 1 and WR = 1 in the flag 73, the flash controller 77 of the control unit 72 recognizes a command to write to the flash memory 11 and cycle cycles. The multiplexer 74 is controlled while the 76 is raised, and the chip enable signal / CE and the write enable bar signal / WE are generated.

In addition, the command generator 75 generates a command according to the flag signal of the flag 73 and writes the data DATA [7: 0] to be written through the multiplexer 74 in the last fourth cycle. It writes to the address (Address [15: 0]) input via 74.

Conversely, the bits of the flag 73 (EN = 1, RD = 1) in order for MCU 10 to read the data DATA [7: 0] of the flash memory 11 through the interface of the flash controller 77. In this case, the flash controller 77 of the controller 72 recognizes a command to read and controls the multiplexer to apply an address signal to the flash memory 11, and to enable the chip enable bar signal / CE and out enable. The bar signal / OE is generated to read data DATA [7: 0] from the flash memory 11.

Similarly, when the chip sets the bit 73 of the flag 73 to EN = 1, CE = 1 when the chip raises (Chip_Erase), the flash controller 77 receives the input and performs a control operation accordingly, that is, the flash controller 77. At the same time, the command generator 75 also generates a laser command signal according to the flag 73 EN = 1, CE = 1. Then, the control signals S1 and S2 of the flash controller 77 are generated. The laser command signal is applied to the flash memory 11 through the multiplexer 74 to erase the chip.

Here, the command signal of the command generator 75 is output in synchronization with the counting signal of the cycle counter 76.

In addition, when the sector erase (Sector_Erase) is set to the flag bits EN = 1 and SE = 1, the command generator 75 transmits the sector erase command signal to the counting signal of the cycle counter 76 by the flag bit as in the read / write operation. In synchronization with the multiplexer 74, and the flash controller 77 receives the flag bit and applies a control signal according to the multiplexer 74 to apply the sector-raise command signal to the flash memory 11. Thus, the sector erase operation is performed.

At this time, the flash controller 77 applies a raise signal / CE and a write enable signal / WE to the flash memory 11.

Here, the ready signal READY is a signal for notifying the MC 10 when the write / read signal and the chip erase / sector erasure are completed.

That is, when the ready signal READY occurs at the time of writing, the MC 10 writes the next 1 byte, and then the MC U after notifying that the chip (Chip_Erase) and the sector erase (Sector_Erase) are finished. 10 performs another operation on the flash memory 11.

As described in detail above, the present invention can reduce the burden of MC oil because the flash memory is controlled by hardware, and the speed is improved because the flash memory is controlled by hardware.

Claims (2)

First and second registers 70 and 71 for storing an address Address [15: 0] and data DATA [7: 0]; A first oar gate OR1 that receives the chip select bar signal / CS and the light bar signal / WR and performs an operation on the chip select bar signal / CS and the write bar signal / WR; A second orifice OR2 that receives the chip select bar signal / CS and the lead bar signal / RD and calculates the result; A flag 73 which receives data DATA [7: 0], an address and a write bar signal, and sets a flag bit accordingly; The operation signals of the first and second OA gates OR1 and OR2 and the flag signals of the flag 73 are input to control command / write and read / write operations of the flash memory and sector / chip laser operations. A control unit 72 for outputting a control signal; And a multiplexer 74 which receives the signals of the first and second registers 70 and 71 and the command signal and transmits them by the control signal of the controller 72. Lead / Light Controller. 2. The control unit 72 according to claim 1, wherein the control unit 72 counts the cycle counter 76 to describe the write command signal, the chip_erase command signal, and the sector_erase command signal by the bit value of the flag 73. A command generator 75 for outputting in synchronization with the signal; A cycle counter 76 for counting clocks from the first cycle to the sixth cycle; And a flash controller (77) for controlling the interface of the flash memory (11) by the bit value of the flag (73).

Images