JPH03246649A - Computer - Google Patents

Abstract

PURPOSE:To make it possible to use a RAM incorporated with a refresh circuit by means of a normal CPU by forming a chip selecting signal for selecting the RAM by the combination of a select signal, a refresh signal and an address strobing signal. CONSTITUTION:The address strobing signal outputted from the terminal ASTB of the CPU 1 is inputted to an R/S flip flop (FF) 7 through an inverter 6 and the refresh signal outputted from a terminal REFRQ is directly inputted to the FF 7. Negative logic-logic product between the output of the FF 7 and the address strobing signal is found out by a gate 8. On the other hand, negative logic-logic products between the output of the gate 8 and select signals outputted from output terminals Y1, Y2 are respectively found out by gates 9, 10. The outputs of respective gates 9, 10 are inputted to the terminals CE of respective RAMs 3, 4. Consequently, the RAM incorporated with the refresh circuit can be used without using an exclusive CPU.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a computer device using a dynamic memory with a refresh circuit added.

[Conventional technology]

Traditionally, dynamic memory and static memory have been used in the storage section of computer equipment, but dynamic memory is often used in computer equipment that requires large storage capacity due to its low cost. . Since refresh is essential for dynamic memory, RAMs that are made into one chip by adding a refresh circuit to dynamic memory have been commercialized. Such a RAM has a terminal that allows access, a terminal that puts it in a write state, and a terminal that puts it in a read state, and the state of the RAM is selected depending on the state of these three terminals. . That is, when access is permitted, the write state or read state is entered when the write state or read state is selected by the respective terminal. On the other hand, when access is not permitted, refreshing is performed if the read state is selected, and precharging is performed if neither the read state nor the write state is selected.

[Problem to be solved by the invention]

By the way, a typical CPU is equipped with a terminal for specifying the read state and write state, but the RAM with the above-mentioned configuration is
Normally, it does not have a terminal for selecting the state of
There was a problem that PU had to be used. The present invention aims to solve the above-mentioned problems, and uses a normal CPU to create a RAM with a built-in refresh circuit.
The aim is to provide a computer device that can be used by

[Means to solve the problem]

In order to achieve the above purpose, in the structure of claim 1!11,
A CP comprising a first terminal that generates an address strobe signal when at least a part of the address bus is shared with a data bus and output of the shared path is used as address information.
and a RAM consisting of a dynamic memory to which a refresh circuit is added, the CPU is equipped with a second terminal that generates a refresh signal at a constant cycle, and the RAM is
The third terminal allows access when a chip select signal is input, and the third terminal enters the read state when a signal is input when access is permitted, and the signal is input when access is not permitted. and the fourth to refresh.
terminal, and access is not permitted and the fourth
When no signal is input to the fourth terminal, precharging is performed, and a refresh signal is input to the fourth terminal, and the period is from when the refresh signal is generated until the next address strobe signal is output. A control circuit is also provided for inhibiting input of the chip select signal to the third terminal during the period when the address strobe signal is being generated. In the configuration of claim 2, the CPU includes a fifth terminal that outputs a read signal instructing reading from the RAM, and the control circuit calculates the logical sum of the delayed refresh signal and the read signal. The signal is input to the fourth terminal.

[Effect]

According to the structure of claim 1, since the timing for refreshing and precharging the RAM can be set using the address strobe signal and the refresh signal that can be output by a normal CPU, the timing for refreshing and precharging the RAM can be set without using a dedicated CPU. A RAM with built-in circuitry can be used. According to the structure of claim 2, since a signal obtained by delaying the refresh signal is inputted to the terminal for selecting refresh of the RAM, access to the RAM is prohibited according to the structure of claim 1. Refreshing is started later, and it is possible to reliably prevent malfunctions caused by the terminal for selecting the read state being used as the terminal for starting refreshing.

【Example】

The CPU used in this embodiment has an address space of 17 bits, and the lower 9 bits of the address bus are shared with the data bus. That is, terminals A8 to A16 output upper address signals indicating the upper 9 bits of the address, and terminals ADO to AD7 output lower address signals indicating the lower 8 bits of the address, and 8-bit data. It can be in the state of inputting and outputting. In this way, terminal AD
Since O to AD7 are commonly used for address information and data, an address strobe signal is output from the terminal ASTB in order to select whether it is address information or data. The CPUI also connects a terminal WR which instructs writing to the memory and a terminal RD which instructs reading.
, a terminal REFRQ for instructing refresh, a terminal CLK for generating a system clock, and terminals X + and X 2 for connecting crystal resonators XL. On the other hand, the memories include one ROM2 and two RA
M3.4, and each is given a different address. ROM2 and RAM3.4 each have a 15-bit address space, and when a chip select signal generated based on the upper two bits of the CPUI address information is input to terminal CE, ROM2 and RAM3.
This makes it possible to input and output data to either AM3 or AM4. The ROM2 includes a terminal OE that instructs data reading when a chip select signal is input to the terminal CE. RAM3゜4 is a dynamic RAM with a built-in refresh circuit, and is connected to terminal C.
It has a terminal WE that instructs data writing when a chip select signal is input to E, and a terminal OE/RF that instructs reading or refreshing. Also, R
OM2 and RAM3.4 have terminals AO to A14 for specifying addresses and terminals DO to D7 for inputting and outputting data.
and is provided. Each terminal WE, O in RAM3.4
The operating status of E/RF, CE and RAM 3.4 is as shown in the table below. When trying to use cput with the above configuration, the CPU
Since the lower 8-bit address bus is shared with the data bus, the following procedure is required to access R10M2 or RAM3.4. That is, first, the address information is output from the CPUI, the lower 8 bits of the address information are held in the latch circuit 14, and the upper 9 bits are continuously output, and then the data corresponding to the specified address is input/output. It has to be done. The latch circuit 14 stores the lower 8 bits of address information, and when the address strobe signal outputted from the terminal ASTB becomes "H", the terminals ADO~
When the output of AD7 is instructed to be address information, the information is stored in the latch circuit 14, and when the address strobe signal is "L", the latch circuit 1
Only 4 types of information can be read. The upper two bits of the address information are input to the decoder circuit 5, and the decoder circuit 5 generates a selection signal to select one of ROM2 and RAM3.4 according to the combination of the two bits of input data. do. That is, the terminal YO
is “L”, ROM2 is selected and terminals Yl, Y2
is "L", selection signals corresponding to RAMs 3 and 4 are output. The chip select signal input to the terminal cE to select the RAM 3.4 is not only the selection signal output from the terminals Yl and Y2 of the decoder circuit 5, but also the refresh signal output from the terminal REFRQ and the input signal from the terminal ASTB. It is created in combination with the output address strobe signal. Next, the selection signal input to the terminal CE of the RAM 3.4 will be explained. The address strobe signal outputted from the terminal ASTB is inputted to the set terminal S of the R-S flip-flop 7 through the inverter 6, and the reset end refresh signal of the R-S flip-flop 7 is inputted. Therefore, when the refresh signal falls and the start of the refresh operation is instructed, the output Q of the R-S flip-flop 7 becomes "H", the address strobe signal rises, and the address information is output from the terminals ADO to AD7. When started, the output Q of the R-S flip-flop 7 is “
In other words, the output of the R-S flip 770 knob 7 becomes low when the address strobe signal falls and the ROM
When access to RAM 2 or RAM 3 or 4 is started, it is kept at "L" until the next refresh is started. The output of R-S flip 70 tube 7 is
Since gate 8 performs a negative logical AND with the address strobe signal, access to ROM2 or RAM3.4 is started, and when data can be input/output at terminals ADO to AD7, then terminal ADO
~The output of gate 8 is “L” until AD7 starts outputting an address or refresh starts.
become. The output of gate 8 is connected to output Y1. of decoder circuit 6 by gate 9.10. A negative logical AND is performed on each of the selection signals output from Y2. Therefore, during the period when the output of the gate 8 is "L" as described above, if the selection signal output from either of the output terminals Y1, Y2 of the decoder circuit 6 becomes "L", the output terminals Yl, Y2 The output of the gate 9.10 corresponding to this becomes "L".The output of each gate 9.10 is inputted to the terminal CE of each RAM3.4 as a chip select signal, so the output of the gate 9.10 corresponding to When data can be input/output in the period other than the refresh period, one of the RAMs 3.4 is selected. On the other hand, the refresh signal output from the terminal REFRQ is input to the data terminal of the D flip-flop 11, and the clock terminal C of the D flip-flop 11
A system clock signal outputted from a terminal CLK of the CPUI is inverted by an inverter 12 and input to K. Therefore, when the refresh signal goes to "L" and a refresh period is designated, the output Q of the D flip-flop 11 occurs at the rising edge of the system clock signal.
The output of the D flip 70 knob 11, which becomes "L", is negative ORed with the read signal output from the terminal RD at the gate 13. The output of gate 13 is
Since it is connected to the terminal OE/RF of M3.4, when the terminal OE/RF becomes "L", it is an instruction to start refreshing or reading data. Whether it is a refresh or a data read is instructed by the state of the terminal CE, and when the terminal CE is "L", data is read. Here, the refresh signal is applied to the RAM at the rising edge of the system clock signal.
Since the data is input to the terminal OE/RF of the RAM 3.4, refreshing is performed after the terminal CE becomes "H" and the prohibited state of access to the RAM 3.4 is established. The operation will be explained below based on the 21ffi and FIG. 3. FIG. 2 is a time chart when the same RAM 3.4 is accessed continuously, and FIG. 3 is a time chart when the same RAM 3.4 is accessed continuously.
4 is a time chart when No. 4 is not accessed. As shown in FIG. 2(g), the CPUI periodically
A refresh signal is output from terminal REFRQ so that a refresh cycle is inserted after the end of a read cycle or a write cycle. When access to the RAM 3.4 is started, as shown in FIG. 2(d), an address strobe signal is output from the terminal ASTB, and during this period, as shown in FIG. 2(c), The signals output from terminals ADO to AD7 are the lower 8 bits of address information. Further, when the address strobe signal is not output, the signals output from the terminals ADO to AD7 become data. As shown in FIG. 2(a), outputs are always obtained from terminals A8 to A16 during one cycle and specify the upper nine bits of address information. In a read cycle, a read signal is output from terminal RD, and in a write cycle, a write signal is output from terminal WR. During the period when the address strobe signal is H"°, the terminal CE of RAM3.4 is always "
H", access to RAM 3.4 is prohibited. Since RAM 3.4 is precharged when access is prohibited, there is a requirement to provide a precharge period before access. On the other hand, when a refresh signal is output from the terminal REFRQ, the terminal CE becomes “
H”, access to RA and M3.4 is prohibited, and access to RAM3.4 is prohibited until the next address strobe signal rises.After that, in synchronization with the rise of the system clock signal, access to RAM3.4 is prohibited. terminal OE
Refreshing is started when /RF becomes "L". Furthermore, when the refresh is completed, the device enters a precharge state. As described above, when the RAM 3.4 is accessed, a precharge period and a refresh period can be reliably provided. Next, when the RAM 3.4 is not accessed, the selection signal is not output from the decoder circuit 5, so as shown in FIG.
As shown in h), the terminal CE of RAM3.4 is always H”
Then, when a read signal is generated from terminal RD to other RAM 34 or ROM 2, RAM 3.4 recognizes that refresh has been instructed, and refresh is performed during this period as well. The other operations are the same as those in FIG. 2, so their explanation will be omitted.

【Effect of the invention】

As described above, in the configuration of claim 1, the present invention includes a first terminal that generates an address strobe signal when at least a part of the address bus is shared with a data bus and the output of the shared bus is used as address information. The CPU is equipped with a second terminal that generates a refresh signal at a constant cycle, and the RAM is accessed when a chip select signal is input. a third terminal that allows access, and a fourth terminal that enters a read state when a signal is input when access is permitted, and refreshes when a signal is input when access is not permitted. and is configured to perform precharging when access is not permitted and no signal is input to the fourth terminal, and a refresh signal is input to the fourth terminal and the refresh signal is generated. A control circuit is provided for inhibiting the input of the chip select signal to the third terminal during the period from 1 to 3 until the next address strobe signal is output and during the period when the address strobe signal is being generated. RAM refresh and precharge timing can be set using the address strobe signal and refresh signal that can be output by a normal CPU, so there is no need to use a dedicated CPU.
It has the advantage that a RAM with a built-in refresh circuit can be used. In the structure of claim 2, the CPU includes a fifth terminal that outputs a read signal instructing reading from the RAM, and the control circuit calculates the logical sum of the delayed refresh signal and the read signal. The signal is input to the fourth terminal, and the signal obtained by delaying the refresh signal is input to the R
Since the input is input to the terminal for selecting refresh of AM, according to the configuration of claim 1, refresh is started after access to the RAM is prohibited, and the terminal for selecting the read state is input. This has the effect of reliably preventing malfunctions caused by the terminal being used as the terminal for starting refresh.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams explaining the same operation. 1...CPU, 2...ROM, 3.4...RAM
, 5... Decoder circuit, 6... Inverter, 7...
・R-S flip-flop, 8 to 10...gate, 1
1...D flip-flop, 12...inverter,
13...gate, 14...latch circuit.

Claims (2)

[Claims] (1) At least a part of the address bus is shared with the data bus, and a CPU is provided with a first terminal that generates an address strobe signal when the output of the shared bus is used as address information, and a refresh circuit is added. The CPU is equipped with a RAM consisting of a dynamic memory, and the CPU is equipped with a second terminal that generates a refresh signal at a constant cycle.
M is a third terminal that permits access when a chip select signal is input, and a third terminal that enters a read state when a signal is input when access is permitted, and a signal that is input when access is not permitted. and a fourth terminal that performs refresh when input, and when access is not permitted and no signal is input to the fourth terminal, precharging is performed, and the refresh signal is refreshed from the fourth terminal.
The chip select signal is input to the third terminal, and during the period from when the refresh signal is generated until the next address strobe signal is output and during the period when the address strobe signal is generated, the chip select signal is input to the third terminal. A computer device comprising a control circuit that prohibits input. (2) The CPU includes a fifth terminal that outputs a read signal instructing reading from the RAM, and the control circuit calculates the logical sum of the delayed refresh signal and the read signal to the fourth terminal. 2. The computer device according to claim 1, wherein the computer device inputs information to a terminal.