JPS607279B2 - Screen memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for rewriting contents stored in a screen memory into a specific code in an extremely short time.

Conventionally, the contents stored in a screen memory are displayed on a cathode ray tube under the control of a microprocessor, and the stored contents are erased when they are no longer needed, as shown in the block diagram of FIG.

In FIG. 1, a screen memory (RAM) is connected to an address bus from a data processing unit, for example, a microprocessor M, via a first multiplexer M, and a direct memory access circuit (DMA circuit) is connected to the first multiplexer. RAM is connected via MPX-1. 1st
In the figure, '1) Writing information to the screen memory RAM ■ Displaying information stored in the screen memory on a display unit using a cathode ray tube {3i Screen memo] The erasing of information on the screen will be explained.

First, for case 1, microprocessor unit M
The information to be stored is input to the PU' via the data bus, and the address on the screen memory RAM is input via the address bus.

As a result, when these are input, the MPU is switched to write mode and outputs the address to the multiplexer M-X-1 and the command register CMR via the address bus, as well as information (actually a code corresponding to the character pattern). ) is applied to the screen memory RAM via the data bus. The command register CM Nagi gives a write command to the multiplexer MPX-1 and the screen memory read/write control circuit, switches the RAM to write mode, and switches the multiplexer MPX-1 to the address bus and the screen memory RA.
command to connect with M.

Therefore, in the screen memory RAM, the multiplexer MPX
The character code given via the data bus is stored at the address on the memory given via -1.

Next, the case of display '2' will be explained. When a display command is input, the multiprocessor MPU is switched to the display mode '2', and the display command is given to the command register CM old via the address bus.

CMR uses multiplexer MPX based on the display command.
-1 so that the direct memory access circuit DMA is connected to the screen memory RAM, and the screen memory RAM is read out via the screen memory read/write control circuit R/W-CC. Circuit D
Give a counting start command to MA. Therefore, addresses are sequentially given from the DMA to the screen memory RAM via the multiplexer MPX-1, and information corresponding to the addresses is sent to a line buffer (not shown) provided in the display control circuit DSC for each line on the display screen. ) is sent. When the display for one line stored in this line buffer is completed, the DMA gives the next address to the screen memory RAM, and similarly sends the character code for one line corresponding to that address to the display control circuit DSC. . Display control circuit DS
C causes a character pattern corresponding to the character code to be displayed on the cathode ray tube display section CRT as a display video signal. Next, glue erasing will be explained.

Erasing is a modification of writing, and erasing includes partial erasing and full erasing. For partial erasure, an address on the screen memory to be erased is given, and it is performed in the same way as writing.
That is, when an erase command is given via the command address by the microprocessor M-U via the address bus, the multiplexer M-X-1 and the screen memory lj read/write control circuit R-W- It commands the CC to erase. Therefore, in the screen memory RAM, the space code (all "OW") given via the data bus is stored in the location corresponding to the address input via the multiplexer M-Kan. .

This completes the erasure of information for one address. In the case of full-screen erasing, there are two modes: line erasing and full screen erasing. In the case of erasing a line, the microprocessor MP inputs the address of the line and a command to erase the line, and the MPU sequentially sends the address of one line from that address to the screen memory RAM via the multiplexer MPX-1.
Subasco via the address bus
Enter the screen memo and delete only that one line.
Next, in the case of erasing the entire screen, when the entire screen erasing command is input to the microprocessor MPU, the MmU sequentially sends addresses to the multiplexer M from the top address on the screen.
It is given to the screen memory RAM via the PX- quantity and '
In synchronization with the sending of that address, the space code is also stored in RAM.
give to

By performing this process up to the final address of the RAM, the entire area is erased. The above is a description of the conventional operation, but the problem here is the erasing time.

In other words, it takes 20 seconds of erasing time for each character, and 20 seconds of erasing time is required for each character.
If the erase operation is approximately 0.0 seconds, it will take about 50 seconds from the start of the erase operation to the end. Furthermore, in the case of a display that is controlled using flags, it takes 100 hours to erase the memory, which is too long compared to the time required for other tasks for the MPU, so it sends a "response signal" to the MPU during processing. The firmware needs to take into account time-over operations when it is mistakenly recognized as a failure, such as sending back data. Hence the microphone. This has a negative impact on the processing efficiency of the processor. Focusing on the fact that these drawbacks arise from the fact that addresses are generated via the microprocessor MPU for line erasure, full screen erasure, etc., the present invention uses direct The memory access circuit DMA is also used as an address generation means in the case of erasing the entire screen as described above. The embodiment of the present invention shown in FIG. 2 will be described below.

The same reference numerals as in FIG. 1 indicate the same things, CDG is a specific code signal generating circuit, in this case a space code generating circuit, MPX-2 is a switching means such as a multiplexer, and a data bus line from the microprocessor MPU is shown. and a data bus line from a specific code signal generation circuit COG are input.

The operation when displaying on a CRT screen is the same as in the case of FIG. When erasing the entire screen, the MPU sends CM via the address bus.
Give a command to the eaves and switch MPX-1 to DMA side, RNOW
- Switch the CC to the write side and operate the DMA to specify from the initial address. At this time, the M-circle X-2 is switched to apply the CDG output to the RAM by a command from the CMR, and the constantly occurring base code (all "0") is written into the RAM. Therefore, the faster the operating time of the DMA circuit that specifies the address of the RAM, the further it is possible to complete the "erase" operation by converting the entire contents of the screen memory into a blank code signal. In the case of line erasure, a line erasure command and the starting address of the line to be erased are input to the microprocessor MPU. Thereby, the command register commands the DMA to generate an address from that address, and stores the space code to be input to the screen memory RAM via multiplexer MPX-2 at the commanded address in the same way as described above. Note that when a circuit that constantly generates specific characters is used instead of the specific code signal generating circuit, the contents of the screen memory can be completely rewritten to specific characters in a very short time and stored, and later displayed on the CRT. In this way, the present invention is equipped with a specific code signal generation circuit and a circuit that switches its output to be applied to the screen memory, and the direct memory access circuit, which was conventionally used only for reading, can be effectively used for writing. By doing so, the contents of the screen memory can be rewritten to a specific code or erased in an extremely short time, and in the experiment using the example described above, results were obtained within 3 seconds.

Therefore, it is extremely effective in practice.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating a conventional screen memory erasing method, and FIG. 2 is a block diagram showing an embodiment of the present invention. MPU...Microprocessor, RAM...
... Screen memory, DMA ... Direct memory access circuit, CRT ... Cathode ray tube, MPX
-1, MPX-2...Multiplexer, CMR...
Command register, CDG...Specific code signal generation circuit, R/W-CC...Screen memory read/write control circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. It has a display section that displays information such as characters, and a line buffer that stores code information corresponding to one line of characters, etc. to be displayed on the display section, and the code information stored in the line buffer is displayed on the display section. a display control circuit that converts the pattern information into pattern information and sends the pattern information to the display section for display in synchronization with the scanning timing of the display section; and a display control circuit that stores code information for one screen corresponding to the display section. A screen memory, a direct memory access circuit that generates at a predetermined timing an address on the screen memory storing code information to be transferred to the line buffer among the code information stored in the screen memory, and a data bus. data processing means for sending arbitrary code information to be displayed to the screen memory; a specific code generation circuit for sending only specific code information to the screen memory via the data bus; and a data bus from the data processing means. and a data bus from a specific code generation circuit, and a switching means for sending the code information supplied to either one of the data buses to the screen memory according to an instruction from the data processing means. When a command arrives, the data processing means instructs the switching means to switch the data bus so that the code information from the specific code generation circuit is sent to the screen memory, and the direct memory access circuit A screen memory control method characterized in that an address is given to the memory, a specific code generation circuit gives specific code information to the screen memory in synchronization with the address, and the specific code information is stored at the address.