JPS5627962A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS5627962A
JPS5627962A JP10372179A JP10372179A JPS5627962A JP S5627962 A JPS5627962 A JP S5627962A JP 10372179 A JP10372179 A JP 10372179A JP 10372179 A JP10372179 A JP 10372179A JP S5627962 A JPS5627962 A JP S5627962A
Authority
JP
Japan
Prior art keywords
integrated circuit
conducting layer
insulating layer
pad
conducting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10372179A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10372179A priority Critical patent/JPS5627962A/en
Publication of JPS5627962A publication Critical patent/JPS5627962A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To effectively perform the noise suppressing measure, by forming a conducting layer for shielding on an integrated circuit element via an insulating layer, and connecting a power-supply pad for the integrated circuit to said conducting layer. CONSTITUTION:A conducting layer 3 is provided on the surface of the integrated circuit in a desired pattern. The uppermost conducting layer 13 is insulated from conducting layers 8 and 9 in the inner circuit by an insulating layer 12, and is conducted only to a ground potential pad 10 through a hole provided in the insulating layer 12, but not conducted to another pad 11. Since the surface of the inner circuit is covered by the electric shield at a constant potential, the noise suppression measure is effectively provided.
JP10372179A 1979-08-15 1979-08-15 Integrated circuit device Pending JPS5627962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10372179A JPS5627962A (en) 1979-08-15 1979-08-15 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10372179A JPS5627962A (en) 1979-08-15 1979-08-15 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5627962A true JPS5627962A (en) 1981-03-18

Family

ID=14361540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10372179A Pending JPS5627962A (en) 1979-08-15 1979-08-15 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5627962A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122776A (en) * 1982-01-14 1983-07-21 Fujitsu Ltd Semiconductor device
JPS60229369A (en) * 1984-04-27 1985-11-14 Hitachi Ltd Semiconductor device
US4628343A (en) * 1982-11-08 1986-12-09 Nec Corporation Semiconductor integrated circuit device free from mutual interference between circuit blocks formed therein
US5150189A (en) * 1986-02-28 1992-09-22 Canon Kabushiki Kaisha Semiconductor apparatus
JP2003068974A (en) * 2001-08-28 2003-03-07 Fujitsu Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103385A (en) * 1977-02-22 1978-09-08 Seiko Instr & Electronics Ltd Integrated circuit for watches

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103385A (en) * 1977-02-22 1978-09-08 Seiko Instr & Electronics Ltd Integrated circuit for watches

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122776A (en) * 1982-01-14 1983-07-21 Fujitsu Ltd Semiconductor device
JPH0412035B2 (en) * 1982-01-14 1992-03-03 Fujitsu Ltd
US4628343A (en) * 1982-11-08 1986-12-09 Nec Corporation Semiconductor integrated circuit device free from mutual interference between circuit blocks formed therein
JPS60229369A (en) * 1984-04-27 1985-11-14 Hitachi Ltd Semiconductor device
US5150189A (en) * 1986-02-28 1992-09-22 Canon Kabushiki Kaisha Semiconductor apparatus
JP2003068974A (en) * 2001-08-28 2003-03-07 Fujitsu Ltd Semiconductor device

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