JPS562769A - Rational number-multiple angle type delay detecting circuit - Google Patents

Rational number-multiple angle type delay detecting circuit

Info

Publication number
JPS562769A
JPS562769A JP7812679A JP7812679A JPS562769A JP S562769 A JPS562769 A JP S562769A JP 7812679 A JP7812679 A JP 7812679A JP 7812679 A JP7812679 A JP 7812679A JP S562769 A JPS562769 A JP S562769A
Authority
JP
Japan
Prior art keywords
phase
delay
circuit
integer
phis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7812679A
Other languages
Japanese (ja)
Other versions
JPS6013631B2 (en
Inventor
Hiroshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54078126A priority Critical patent/JPS6013631B2/en
Publication of JPS562769A publication Critical patent/JPS562769A/en
Publication of JPS6013631B2 publication Critical patent/JPS6013631B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2092—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To simplify the processing of a detection signal, by utilizing the frequency division function dependent upon a frequency dividing circuit and a function equivalent to multiplication dependent upon combination of a delay detecting circuit and a multiplying circuit to make the phase in delay detection into a rational integer easily. CONSTITUTION:Angle modulation input signal phis(t) is divided to 1/P by 1/p (P is a natrual number) frequency dividing circuit 1 to generate the output of the second angle modulation signal phis(t)/P. This signal phis(t)/P is applied to delay circuit 2 where delay T+gammam is set by the m-th delay circuit terminal to output q- number delay phase signals to which the fixed phase consisting of the phase sum between an arbitrary phase and the phase of k-multiplied (k is an integer O-q-1) pi/q radian (q is an integer of 2 or more) is added. Phase difference between respective delay phase singnals and signal phis(t)/P are applied to q-number delay detecting circuits 3-1-3-q to detect phase difference between both signals, and the phase in delay detection is made into a rational integer easily and is applied to multiplying circuit 4 and is processed.
JP54078126A 1979-06-22 1979-06-22 Rational multiple square delay detection circuit Expired JPS6013631B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54078126A JPS6013631B2 (en) 1979-06-22 1979-06-22 Rational multiple square delay detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54078126A JPS6013631B2 (en) 1979-06-22 1979-06-22 Rational multiple square delay detection circuit

Publications (2)

Publication Number Publication Date
JPS562769A true JPS562769A (en) 1981-01-13
JPS6013631B2 JPS6013631B2 (en) 1985-04-08

Family

ID=13653183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54078126A Expired JPS6013631B2 (en) 1979-06-22 1979-06-22 Rational multiple square delay detection circuit

Country Status (1)

Country Link
JP (1) JPS6013631B2 (en)

Also Published As

Publication number Publication date
JPS6013631B2 (en) 1985-04-08

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