JPS55127668A - Multiplier - Google Patents

Multiplier

Info

Publication number
JPS55127668A
JPS55127668A JP3445079A JP3445079A JPS55127668A JP S55127668 A JPS55127668 A JP S55127668A JP 3445079 A JP3445079 A JP 3445079A JP 3445079 A JP3445079 A JP 3445079A JP S55127668 A JPS55127668 A JP S55127668A
Authority
JP
Japan
Prior art keywords
input
switch
negative
circuit
invert
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3445079A
Other languages
Japanese (ja)
Inventor
Shigenori Kawamura
Tomohiko Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP3445079A priority Critical patent/JPS55127668A/en
Publication of JPS55127668A publication Critical patent/JPS55127668A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce errors of a multiplier to one fourth by improving the constitution of a circuit which multiplies one input value by the other.
CONSTITUTION: Two input values from input terminals 1 and 2 are applied to (2 by absolute value -1) circuits 3 and 4, whose output values are multiplied by each other by multiplying circuit 5, and the negative multiplication output numeral of the multiplication value, inverted output values obtained by passing the outputs of circuits 3 and 4 through inverting amplifiers 6 and 7, and "-1" applied to bias input terminal 8 are added together and divided by four by divider 18 before being applied to analog switches 13 and 14. On the other hand, the outputs of comparators 9 and 10 are applied to switches 13 and 14 by way of EX-OR circuit 11 and inverter 12 according to the positive or negative sign of two input numerals to exercise control. Then when the input numerals are both positive or negative, switch 13 is turned ON, and switch 14 OFF to invert the signs by inverting amplifier 15 before transmission to output terminal 17, and when the both differ in sign, switch 13 is turned OFF, and switch 14 ON to invert the signs by inverting amplifiers 15 and 16, thereby sending them out to output terminal 17.
COPYRIGHT: (C)1980,JPO&Japio
JP3445079A 1979-03-26 1979-03-26 Multiplier Pending JPS55127668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3445079A JPS55127668A (en) 1979-03-26 1979-03-26 Multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3445079A JPS55127668A (en) 1979-03-26 1979-03-26 Multiplier

Publications (1)

Publication Number Publication Date
JPS55127668A true JPS55127668A (en) 1980-10-02

Family

ID=12414578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3445079A Pending JPS55127668A (en) 1979-03-26 1979-03-26 Multiplier

Country Status (1)

Country Link
JP (1) JPS55127668A (en)

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