JPS5627453A - Address control system - Google Patents

Address control system

Info

Publication number
JPS5627453A
JPS5627453A JP10191679A JP10191679A JPS5627453A JP S5627453 A JPS5627453 A JP S5627453A JP 10191679 A JP10191679 A JP 10191679A JP 10191679 A JP10191679 A JP 10191679A JP S5627453 A JPS5627453 A JP S5627453A
Authority
JP
Japan
Prior art keywords
contents
program
instruction
address
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10191679A
Other languages
Japanese (ja)
Inventor
Hitoshi Takase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10191679A priority Critical patent/JPS5627453A/en
Publication of JPS5627453A publication Critical patent/JPS5627453A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the number of program steps by providing programmable logic array PLA that receives conditional flag contents and contents corresponding to program steps.
CONSTITUTION: Instruction decoder 4 sends program branch instruction JUM to PLA output part 11. Then, PLA8 receives respective bit contents of flag register 9 and step register 10 and generates the address of a program branch destination, determined in accordance with the combinational state of conditional flag contents, through logic constitution. Output part 11 performs OR in terms of respective output line signals of PLA8 and outputs the OR output as the address contents of the branch destination by instruction JUM. This output signal is supplied to address register 2 by way of multiplexer 7, completing branch processing. Therefore, the processing is performed by the single branch instruction and the number of program steps is decreased, which is useful for a microcomputer whose program size is limited.
COPYRIGHT: (C)1981,JPO&Japio
JP10191679A 1979-08-09 1979-08-09 Address control system Pending JPS5627453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10191679A JPS5627453A (en) 1979-08-09 1979-08-09 Address control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10191679A JPS5627453A (en) 1979-08-09 1979-08-09 Address control system

Publications (1)

Publication Number Publication Date
JPS5627453A true JPS5627453A (en) 1981-03-17

Family

ID=14313225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10191679A Pending JPS5627453A (en) 1979-08-09 1979-08-09 Address control system

Country Status (1)

Country Link
JP (1) JPS5627453A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01224836A (en) * 1988-03-04 1989-09-07 Nippon Hoso Kyokai <Nhk> Processor controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01224836A (en) * 1988-03-04 1989-09-07 Nippon Hoso Kyokai <Nhk> Processor controller

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