JPH01224836A - Processor controller - Google Patents

Abstract

PURPOSE:To automatically obtain a jump address by controlling an address control part by plural condition codes obtained from a controlled object part, generating respective branch addresses set in advance corresponding to respective conditions formed by the condition code, and supplying them to a program memory. CONSTITUTION:An address control part 200 to issue an address to a program memory 100 and a controlled object part, to which program data from the program memory 100 are supplied are provided. Then, a means to control an address control part 200 by plural condition codes obtained from the controlled object part, to output respective branch addresses set in advance corresponding to respective conditions formed by the condition code, and to supply them to the program memory 100 are provided. Thus, the condition code from the controlled object part is always checked, the branch address corresponding to the respective conditions are obtained automatically corresponding to the respective conditions of the condition code, and updating a program step especially is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a processor control device that is effective when installed inside a digital signal processing LSI used for real-time processing of video signals, for example.

(Prior Art) For example, when performing video signal processing, when a horizontal synchronization signal or a vertical synchronization signal arrives, the signal processing process often changes significantly. For example, when a digital address indicating the address of a video signal is generated, when a horizontal synchronization signal arrives, the routine jumps to the routine necessary for the synchronization signal period, and, for example, data is rewritten, etc., and when the scanning period starts, It is necessary to generate an address from the initial value again. Furthermore, when a plurality of video signals are partially inserted into a certain video signal, a situation arises in which the gain control state must be switched in order to adjust the level depending on the video signal to be inserted. In this case, the jump destination address is
It is often determined after evaluating multiple conditions.

(Problem to be solved by the invention) If a method is adopted in which a routine jumps to a routine different from the current routine after determining multiple conditions as described above, the number of steps in the program increases and the determination step is passed. This is not preferable as a real-time processing circuit because the video signal is dropped during the period.

Therefore, the present invention has developed a processor that has a structure that allows the condition code to be checked at all times even during program execution, so that a jump address can be automatically obtained according to the contents of the condition code without waiting for the judgment. The purpose is to provide a control device.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes an address control section that provides an address to a program memory, and a controlled object section that is given program data from the program memory. and means for controlling the address control unit using a plurality of condition codes obtained from the controlled target unit, outputting preset branch addresses according to each state formed by the condition codes, and providing the output to the program memory. It is equipped with the following.

(Function) With the above means, the condition code from the controlled object part is always checked, and the branch address corresponding to each condition is automatically obtained according to each condition code state, and the program step is not necessary. There is no need to update.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of the present invention, and 100 is an external program memory that stores programs. memory 1
A read address of 00 is given from an address control section 200 configured inside the LSI. Address control section 20
0 is the jump address table 201. switching circuit 2
02°203, address latch circuit 204. It is constituted by a program counter 205.

The address control unit 200 can automatically generate the next address at the cycle of the system clock. In other words, the output address of the address latch circuit 204 is given to the external memory 100 as a brief fetch address, and is incremented by 1 by the address counter 205 to become the next address.
It is latched to 04.

External memory 1 read by brief fetch address
Program data from 00 is given to the controlled object.

For example, a flag in an arithmetic unit or a condition code based on horizontal synchronization or vertical synchronization is obtained from the controlled object, and condition 1 or 2 is satisfied. For example, when the instruction at address 10 of the external memory 100 is executed, and then the instruction at address 11 is executed by brief fetch, if condition 1 is satisfied and a branch is to be made, the switching circuit 203 is controlled, For example, a jump address Adl from the address table 201 is latched into the latch circuit 203. Here, if the address is, for example, address 40 in the external memory 100, the address to be fetched next is address 41. To accomplish this, switching circuit 203 then outputs the output of program counter 205;
In other words, the address latch circuit 204 latches address 40+1-41. As a result, the next instruction will be used starting from the one at address 41 of the external memory 100.

After such program branch processing is completed,
Proceed to the original brifetch processing.

In the above description, an example has been described in which a branch occurs by − degrees, but it is also possible to deal with a case where a condition for further branching is satisfied when an instruction output from the program table 600 is executed. In this case, jump address table 201
A plurality of instructions are stored in advance in the address Ad2, and the address Ad2 is latched into the latch circuit 204 depending on the combination of condition codes from the controlled object (for example, condition 2).

FIG. 2 shows the circuit of FIG. 1 in more detail.

The address control section 200 of the external memory 100 includes a jump address table 201, switching circuits 202, 203, .
Latch circuit 204. It is composed of a program counter 205 and the like. Further, the program table section 600 has, for example, eight tables, and which table's program is to be read is determined by a command from the decoder section 500. Furthermore, the multiplexer section 300
has a switching circuit 301 that switches and selects program data from the program table unit 600, and a switching circuit 302 that selects and switches between the output from the switching circuit 301 and the output from the external memory 100. In addition to the decoder 501, the decoder unit 500 also stops the change in the output address of the address control unit 200, and stops the input clock of each latch unit in order to keep the command of the instruction latch unit 400 constant. There is a clock control unit 502 that can perform the following steps.

Now, the control code from the decoder section 500 is as shown in the figure.
(2), (2), (2), (2), (2), Aα, and Ad, and the address data of each part is Adl to Ad8 as shown in the figure, and the instruction data is D al -D a6.

FIG. 3 shows a sequence for reading instructions by normal brifetch. For example, three clock cycles are required before the instruction at address a is executed, and there are steps such as fetching the instruction at address a, decoding the instruction at address a, and executing the instruction at address a. Here, since prefetching is performed, when the instruction at address a is being decoded, the instruction at address b is fetched. In this way, programs can be read and executed without interruption. The next instruction is fetched while the previous instruction is being decoded.
The program counter 205 processes Ad6+1, and Ad4. This is because Ad5 forms the address of the next instruction.

To obtain the above sequence, the decoder 501 outputs the output A of the program counter 205 in the switching circuit 203.
d4 is selected, and the switching circuit 302 controls the program data Da4 from the external memory 100 to be selected.

The decoder 501 generates control codes ■ and ■ according to the condition codes X1 and X2 and the contents of the decode.

Determine ■, ■, ■, Aα, and Ad.

The instructions for controlling the above sequencer include the following instructions.

DO: White address loop (repeat the same command) CONT
:Next address branch (Proceed to the instruction at the next address.) JMP: Branch instruction (Proceed to the instruction at the jump destination.) These instructions are Do/C0NT/JMP.

These three operations are used in combination, such as Do/JMP/JMP, and these three operations have condition codes Xi, X
Determined by 2.

For example, for Do/C0NT/JMP commands, (1)
When condition code Xi and X2 are not established...DO (2) When condition code X1 is established...
0NT (3) When condition code X2 is established...
JMP (4) When both condition codes Xi and X2 are established...Decoded as a C0NT command.

The operations when DO, C0NT, and JMP are established will be individually explained below.

DO Instruction FIG. 4 shows a sequence when, for example, the instruction at address 1 is a Do instruction. The instruction at address 1 is latch section 4
When latched to 00 and decoded, the latch circuit 20
Address Ad6 of No. 4 fetches the instruction at address No. 2. However, at this time, the clocks applied to the latch section 400 and the latch H2O4 are stopped by the clock control circuit 502. For this purpose, the command given to the decoder 501 is 1
The address command is maintained, and the address Ad6 also maintains the contents for address 2 fetch. As a result, decoding and execution of the 1st address instruction held in latch section 400 continues. To move from this state to another state, for example, a condition code is input. At that time, the instruction at address 2 is decoded and executed.

This command is effective, for example, when performing the same processing on all pixel data, and only one command is required.

C0NT instruction This instruction is the same as the operation explained in Figure 3 above,
The addresses a, b, c, and d in FIG. 3 are consecutive addresses.

JMP instruction This instruction uses instructions previously stored in the program table 600 to prevent interruption of instructions during a jump operation.

FIG. 5 shows an example of a sequence during a jump operation.

If a, b, c, etc. are consecutive addresses and, for example, a jump instruction is established when the instruction at address b is decoded, the program data in the program table 600 is output while the instruction at address b is being executed. be done. Furthermore, the switching circuits 301 and 302 are controlled by the control codes ■ and ■, and the data from the program table 600 is transferred to the latch section 4.
It is latched to 00. In the address control unit 200, an address for reading the C address instruction is generated, but while the instruction at the jump address (for example, address 40) is decoded,
The brief fetch address is replaced by address (40+1). In the case of a jump instruction, this is the control code Aα,■
, ■ jump address table 201. This is because the switching circuits 202 and 203 are controlled, and the address at address 41, which is stored in advance in the jump address table 201, is latched into the latch circuit 204.

As a result, when the instruction at address 40 is executed, it means that the instruction at address 41 has been decoded, and brief fetches can be obtained continuously.

If the jump address (address 40) of the external memory 100 is accessed without using the program table 600, the instruction at address b must be decoded and the instruction at address 40 must be fetched from point X in the figure, where the decoding result is known. . In this case, the period t is the external memory 10
It is not possible to fully satisfy the access time of 0, resulting in data errors and the like.

As the jump destination, various jump addresses can be set by decoding output immediately before the jump. Various program data are stored in advance in the program table 600, and the corresponding next address is set in the jump address table. 201 and select it depending on the decoded content.

In the above description, each DO, C0NT, and JMP command was explained individually. However, when the system actually operates, it operates by a combination of the above instructions.

For example, when using the Do/C0NT/JMP command, the process shown in FIG. 6 is effective when performing the processing shown in FIG.
In the case of inserting 2, processing is shown for multiplying by a multiplier in order to equalize the gains of both. α to video signal A2
, if the video signal B2 is multiplied by a multiplier of β, the video signal A2 is multiplied by α in step s01, and it is determined whether the video signal B2 has been input (step s02). If the video signal B2 is not input, it is determined whether there is horizontal synchronization (step 803), and if there is no horizontal synchronization, the process returns to Stella 1S. When the video signal B2 is input in step s02, the video signal B2 is multiplied by the multiplier β (step 5
04), determine whether there is horizontal synchronization (step 5)
05). If there is no horizontal synchronization here, the process returns to step s02 (CONT). If horizontal synchronization is obtained in steps s03 and s05, the process jumps to processing for changing the multiplier, etc., which is necessary during the synchronization period (JMP). When this process is finished, the process described above can be continued by returning to step sol. As the judgment output of step s02,
For example, the determination can be made based on a flag obtained as a result of comparison by the arithmetic unit, and this may be used as the first condition code, and the synchronization signal may be used as the second condition code. In this way, by accessing one instruction once, multiple processing functions can be realized by using condition codes.

Next, for example, in the case of a DO/JMF'/JMP command, the relationship between the conditions and the command is as follows.

(1) When both condition codes Xi and X2 do not hold...DO (2) When condition code x1 holds 0. .

JMP (3) When condition code X2 is established...
JMP (4) When condition codes Xi and X2 are both established...JMP In this case, set the jump destination address to each (2).

If condition (3) is met, if you set different addresses, there will be 3 branches (
One is obtained when there is a Do all command). In the case of condition (4), one of the two jump destination addresses takes priority.

For example, assume that the instruction at address a is Do/JMP/JMP, the first jump destination is address 40, and the second jump destination is address 50, for example. At this time, the addresses Adl and Ad2 of the jump address table 201 are set to 41.
The address and address 51 are set. In the program table 600, a 40th address instruction and a 50th address instruction are stored in advance.

For example, when the condition code X1 is established (for example, in response to the flag of the arithmetic unit) while executing the Do all instruction own address loop (explained in Figure 4), the program jumps to address 40 as explained in Figure 5. , condition code X
When 2 is established (synchronization signal arrives), it jumps to address 50. This is effective, for example, when generating an address in synchronization with a synchronization signal and also generating an address for a video signal. For example, in order to generate an address for obtaining a triangular wave from the initial value to the maximum (MAX) as shown in FIG. 7(a), processing as shown in FIG. 7(b) is required.

That is, an initial value is given to obtain an initial address (step sl). Next, the increment is added to the initial address (step s2), and a comparator determines whether the value PA exceeds the maximum value (step s3). If the maximum value has not been reached, it is determined whether horizontal synchronization has arrived (step s4). If horizontal synchronization has arrived, step S
1, and if it has not arrived, the process moves to step S2. If PA has reached the maximum value in step s3, it is set to PA-0 in step s5 and it is determined whether horizontal synchronization has arrived (step s6). If horizontal synchronization has not arrived, the process returns to step S1. When horizontal synchronization occurs, the process branches to step s7. By performing such processing, it is possible to generate video signal addresses that change with various triangular waves as shown in FIG. 2(a).

The loop of steps 82.83 and 85.86 corresponds to all Do commands, and when horizontal synchronization occurs in step s4 or S6, it corresponds to condition 1 (first JMP command), and in step S4 horizontal synchronization □ If there is no command, this corresponds to condition 2 (second JMP command).

When the address waveform shown in figure (a) is generated continuously,
When horizontal synchronization has arrived, the program at the first jump destination may perform processing such as data rewriting or calculation required during the synchronization signal period, and then return to step sl. Figure (a) shows an example in which the address waveform is phase synchronized with the horizontal synchronization, and an example in which the address waveform is phase shifted by 1/2 in the horizontal period.To obtain such a waveform, the initial value in step s1 and the step Reference value at s2 (P
This is possible by changing A).

Next, an example of a video signal processing system using the above-described sequencer will be explained.

In FIG. 8, two 17-bit external video signals AI and Bl can be input to the network section 2o. In addition to this, 17-bit input sections are prepared, making 32 in total.

The network unit 20 includes a plurality of (for example, 17x48)
It has a 7-bit output section, and for example, the 17th to 48th output sections are grouped into two sets and each set is connected to the programmable arithmetic processing sections 21 (01) to 21 (16), respectively. Programmable arithmetic processing unit 21 (01) to 2
1 (1B) are respectively connected to, for example, the 17th to 32nd input sections of the network section 20. The network section 20 is provided with an output section for obtaining a final video output. There are multiple output sections (
For example, from the 1st to the 16th network section), and can be connected to a similar network section at the next stage.

A main control section 22 provides control signals to the network section 20 and the arithmetic processing sections 21 (01) to 21 (1B).

The input digital signal format handled by the above system is 17 bits in total, as shown in Figure (b), of which 1 bit is used as synchronization signal information, and the remaining bits are used as video signal data or synchronization signal. It is data. When the synchronization signal information is "1", the remaining 16 bits are synchronization signal data, and when it is "0", the remaining 16 bits are video signal data.

Further, the network section 20 has nine LSIs connected to one
The 17-bit input section and the 17-bit output section each have 2 bits assigned to each LSI. In this way, an increase in the number of terminals on one LSI is prevented. Further, the network section 20 has a built-in network control section, and the input/output connection system can be programmably switched by a command from the main control section 22 or the arithmetic processing section.

FIG. 9 shows one of the arithmetic processing units, for example 21 (01).

Depending on its control state, the network section 20 transmits the external video signals A1 and B to the arithmetic processing section 21 (01).
Alternatively, the video signal fed back from the calculation processing section 21 (01) or another calculation processing section can be supplied bare to this calculation processing section 21 (01), or only one video signal can be supplied.

The arithmetic processing unit 21 (Of) receives the video signal A2. It has two input sections that accept B2, and each input section is connected to a synchronization separation section 31A.
, 31B. Synchronization separation section 31A, 31B
The synchronization signal separated by is input to the sequencer 37,
It is used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), and the video signal A2. Used for time adjustment of B2.

The 16-bit video data separated by the synchronization separation sections 31A and 31B can be input to the multiplication section 32 and the calculation section 33. The multiplier 32 can multiply two video signals or can multiply one video signal by a constant or a variable value. The arithmetic unit 33 can add, subtract, or compare two video signals, add or subtract a certain value to one video signal, or perform a comparison process with a certain value.

The outputs obtained by the multiplier 32 and the arithmetic unit 33 can be further supplied to one input of each other, and
Also supplied.

The switching unit 34 selects and outputs one of the inputs, and the output thereof is derived via the synchronization adding unit 35. The synchronization adding section 35 can add or stop a synchronization signal.

This arithmetic processing section 21 (01) is further provided with a synchronization signal processing section 36 and an address generation section 38.

Furthermore, a control memory 41 is also included in addition to the external program memory. control memory 4
1 is designed so that when each data processing section inside the arithmetic processing section 21 (Of) performs its own assigned processing, it is not necessary to read out all instructions from the program memory each time. A unique program can be stored in advance.

FIG. 10 shows an example of combining video signals using the above system. In this case, the network section 20 operates from the arithmetic processing sections 21 (01) to 21 (0
If the connection form of 3) is set as shown in the figure, the external video signal A
An output obtained by adding and combining 1 and 81 can be obtained. The video signal A1 is input to the multiplier of the arithmetic processing unit 21 (01) and multiplied by α, and the video signal B1 is input to the multiplier of the arithmetic processing unit 21 (02).
) is input to the multiplier and multiplied by (1-α). The output of each multiplier is input to the arithmetic processing unit 21 (03), and is added and derived in the arithmetic unit. The network section 20 and the arithmetic processing sections 21 (01) to 21 (1B) can be switched to various forms depending on their processing purpose.

When each of the arithmetic processing units described above performs its own video signal processing, the sequencer described above is effectively used, and real-time processing of the video signal can be smoothly obtained when accessing instructions.

[Effects of the Invention] As described above, the present invention has a configuration in which the condition code can be checked at all times even during program execution, and the jump address is automatically set according to the content of the condition code without waiting for its determination. A circuit that is effective for real-time processing is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a further embodiment of the circuit in FIG. 1, and FIG.
5 to 5 are sequence explanatory diagrams shown to explain an example of the operation of this invention device, FIGS. 6 and 7 are explanatory diagrams showing an example of signal processing executed by this invention device, and FIG.
Figure (a) is an explanatory diagram showing the overall configuration of the device using this invention, Figure (b) is a diagram showing the signal format, Figure (c
) is a diagram shown to further explain the network section, FIG. 9 is a block diagram showing the configuration of the arithmetic processing section in FIG. 8, and FIG. 10 is an explanatory diagram showing an example of the signal processing/form according to the present invention. be. 100...External memory, 200...Address control unit, 201...Jump address table, 201゜2
03...Switching circuit, 204...Latch circuit, 20
5...Program counter. Applicant's agent Patent attorney Takehiko Suzue Figure 6 ゛Horizontal ITI Figure 7 x (1-α) Figure 10 (a) 8th 7bit (b)

Claims (1)

[Claims] an address control unit that provides an address to a program memory; a controlled target unit that receives program data from the program memory; and a plurality of condition codes obtained from the controlled target unit to control the address control unit; A processor control device characterized by comprising means for generating preset branch addresses in accordance with each state formed by the condition code and providing them to the program memory.