JPH01224837A - Processor controller - Google Patents

Abstract

PURPOSE:To satisfy with one instruction to a signal which is satisfied with the same processing such as a picture element, for instance, by providing a decoder part to decode the instruction latched to an instruction latching part, to control a control part to give a clock to the instruction latching part corresponding to the decode content and to stop the clock. CONSTITUTION:A control part, which gives a clock to an instruction latching part 400 to fetch the instruction read out of a program memory 100 by an address control part 200 only when the instruction is changed and stops the clock when the instruction is not changed, is provided. Thus, since the clock of the instruction latching part 400 is stopped when it is satisfied with the same instruction by the output conditions of a decoder part 500, it becomes a repeating instruction automatically, and updating a program step especially is not needed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a processor control device that is effective when installed inside a digital signal processing LSI used for real-time processing of video signals, for example.

(Prior Art) For example, when video signal processing is performed using an arithmetic processing unit, the same processing is very often performed on all pixel data. For example, there are cases where color control information is captured during a burst period and gain control is performed using the same control signal until the next burst period. If such processing is performed using the usual concept of an arithmetic processing unit, program steps will be prepared for every pixel, but it is wasteful to prepare a large number of exactly the same instructions.

(Issues to be Solved by the Invention) As described above, according to the conventional processor control circuit, a large number of steps of exactly the same instruction may be prepared, which wastes memory space.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a processor control device that requires only one instruction for signals that require the same processing, such as pixels.

[Structure J of the Invention (Means for Solving the Problems) This invention provides a clock only when an instruction changes to an instruction latch unit that receives an instruction read from a program memory by an address control unit, A control section is provided that stops the clock when the command does not change.

(Function) With the above means, when the same instruction is acceptable due to the output condition of the decoder section, the clock of the instruction latch section is stopped, so the instruction is automatically repeated, and there is no need to take the trouble of updating the program step (execution). Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of the present invention, and 100 is an external program memory that stores programs. memory 1
A read address of 00 is given from an address control section 200 configured inside the LSI. Address control section 20
0 is multiplexer 101. Address latch section 102
and an address counter 103. The address control unit can automatically generate the next address at the cycle of the system clock. That is, the output address of the address latch section 102 is given to the external memory 100 as a brief fetch address, and is incremented by 1 by the address counter 103 to become the next address, which is latched into the address latch section 102 via the multiplexer 101.

External memory 1 read by brief fetch address
Program data from 00 to multiplexer 300
The command latch unit 400 latches the command through the command latch unit 400. The program data latched here is decoded by the decoder section 500 and given to the controlled section.

Here, the decoder unit 500 decodes the instruction and determines whether the instruction and condition codes X1 and X2 satisfy a certain condition. As a result of the determination, if the next instruction to be executed is not at the pre-fetch address in the external memory 100 but at the jump address, the multiplexer 300 is controlled and the program data from the program table section 600 is The instruction is given to the instruction latch unit 400. This allows the decoder section 500 to obtain desired program data without passing through the jump step in the address control section. For example, when the instruction at address 10 of the external memory 100 is executed, and then the instruction at address 11 is executed by brief fetch, if the condition is met and a branch occurs, the multiplexer 300 is controlled and the Begins execution of the instruction. Here, if this instruction is, for example, the instruction at address 40 of the external memory 100, the next instruction to be executed is the instruction at address 41. In order to achieve this, the decoder section 500 further sends address 40+1-41 to the address latch section 10 through the multiplexer 101.
Latch it to 1. As a result, the next instruction will be used starting from the one at address 41 of the external memory 100.

After such program branch processing is completed,
Proceed to the original brifetch processing.

In the above description, an example has been described in which a branch occurs by − degrees, but it is also possible to deal with a case where a condition for further branching is satisfied when an instruction output from the program table 600 is executed. In this case, a plurality of instructions may be stored in the program table section 600 in advance, and the instruction may be selected based on the decoding result of the decoder 500.

In the program table section 600 described above, jump destination instructions are stored in advance. With such an instruction processing method, the advance control function is fully utilized and seamless execution can be achieved.

Furthermore, the decoder section 500 is provided with a clock control section 502, which is a feature of the present invention, and can stop the clock applied to the instruction latch section 400 under certain conditions. When the clock is stopped, the instruction in the instruction latch unit 400 remains unchanged, and the same processing continues.

FIG. 2 shows the circuit of FIG. 1 in more detail.

The address control section 200 of the external memory 100 includes a jump address table 201, switching circuits 202, 203, .
Latch circuit 204. It is composed of a program counter 205 and the like. Further, the program table section 600 has, for example, eight tables, and which table's program is to be read is determined by a command from the decoder section 500. Furthermore, the multiplexer section 300
has a switching circuit 301 that switches and selects program data from the program table unit 600, and a switching circuit 302 that selects and switches between the output from the switching circuit 301 and the output from the external memory 100. In addition to the decoder 501, the decoder section 500 also stops the change in the output address of the address' control section 200, and stops the input clock of each latch section in order to keep the command of the instruction latch section 400 constant. There is a clock control unit 502 that can perform the following steps.

Now, the control code from the decoder section 500 is as shown in the figure.
Assume that (1), (2), (2), (2), (2), Aα, and Ad, and the address data of each part is Adl-Ad6 as shown in the figure, and the instruction data is Dal-Da6.

FIG. 3 shows a sequence for reading instructions by normal brifetch. For example, three clock cycles are required before the instruction at address a is executed, and there are steps such as fetching the instruction at address a, decoding the instruction at address a, and executing the instruction at address a. Here, since prefetching is performed, when the instruction at address a is being decoded, the instruction at address b is fetched. In this way, programs can be read and executed without interruption. The next instruction is fetched while the previous instruction is being decoded.
The program counter 205 processes Ad6+1, and Ad4. This is because Ad5 forms the address of the next instruction.

To obtain the above sequence, the decoder 501 outputs the output A of the program counter 205 in the switching circuit 203.
d4 is selected, and the switching circuit 302 controls the program data Da4 from the external memory 100 to be selected.

The decoder 501 generates control codes ■ and ■ according to the condition codes X1 and X2 and the contents of the decode.

Determine ■, ■, ■, Aα, and Ad.

The following commands are used to control the above sequencer.

DO = own address loop (repeat the same command) CONT
:Next address branch (Proceed to the instruction at the next address.) JMP: Branch instruction (Proceed to the instruction at the jump destination.) These instructions are Do/C0NT/JMP.

These three operations are used in combination, such as Do/JMP/JMP, and these three operations are condition code X1. X
Determined by 2.

For example, for Do/C0NT/JMP commands, (1)
When condition codes Xi and X2 are not satisfied...D.

(2) When condition code X1 is established...
0NT (3) When condition code X2 is established...
JMP (4) When both condition codes Xi and X2 are established...decoded as a CONT command.

The operations performed when DO, C0NT, and JMP are established will be individually explained below.

DO Instruction FIG. 4 shows a sequence when, for example, the instruction at address 1 is a DO instruction. The instruction at address 1 is latch section 4
When latched to 00 and decoded, the latch circuit 20
Address Ad8 of No. 4 fetches the instruction at address No. 2. However, at this time, the clocks applied to latch section 400 and latch section 204 are stopped by clock control circuit 502. For this purpose, the command given to the decoder 501 is 1
The address command is maintained, and the address Ad6 also maintains the contents for address 2 fetch. As a result, decoding and execution of the instruction at address 1 held in latch unit 400 continues. To move from this state to another state, for example, a condition code is input. At that time, the instruction at address 2 is decoded and executed.

This command is effective, for example, when performing the same processing on all pixel data, and only one command is required.

C0NT instruction This instruction is the same as the operation explained in Figure 3 above,
The addresses a, b, c, and d in FIG. 3 are consecutive addresses.

JMP instruction This instruction uses instructions previously stored in the program table 600 to prevent interruption of instructions during a jump operation.

FIG. 5 shows an example of a sequence during a jump operation.

If a, b, c, etc. are consecutive addresses and, for example, a jump instruction is established when the instruction at address b is decoded, then while the instruction at address b is being executed, the program data file in the program table 600 is Output. Further, the switching circuits 301 and 302 are controlled by the control codes ① and ②, and data from the program table 600 is latched into the latch section 400. In the address control unit 200, C
An address for reading the address instruction is generated, but while the instruction at the jump address (for example, address 40) is decoded, the prefetch address is replaced by address (40+1). In the case of a jump instruction, this is the control code Aα,
Jump address table 201. This is because the switching circuits 202 and 203 are controlled, and the address at address 41, which is stored in advance in the jump address table 201, is latched into the latch circuit 204.

As a result, when the instruction at address 40 is executed, it means that the instruction at address 41 has been decoded, and brief fetches can be obtained continuously.

If the jump address (address 40) of the external memory 100 is accessed without using the program table 600, the instruction at address b must be decoded and the instruction at address 40 must be fetched from point X in the figure, where the decoding result is known. . In this case, the period t is the external memory 10
It is not possible to fully satisfy the access time of 0, resulting in data errors and the like.

As the jump destination, various jump addresses can be set by decoding output immediately before the jump. Various program data are stored in advance in the program table 600, and the corresponding next address is set in the jump address table. 201 and select it depending on the decoded content.

In the above description, each DO, C0NT, and JMP command was explained individually. However, when the system actually operates, it operates by a combination of the above instructions.

For example, when using the DO/C0NT/JMP command, it is effective when performing the processing shown in Fig. 6.
In the case of inserting 2, processing is shown for multiplying by a multiplier in order to equalize the gains of both. α to video signal A2
, the video signal B2 is multiplied by a multiplier of β, the video signal A2 is multiplied by α in step sol, and it is determined whether the video signal B2 has been input (step 502). If the video signal B2 is not input, it is determined whether or not there is horizontal synchronization (step 803); if there is no horizontal synchronization, the process returns to step sol. When the video signal B2 is input in step s02, the video signal B2 is multiplied by the multiplier β (step 8
04), determine whether there is horizontal synchronization (step s
05). If there is no horizontal synchronization, the process returns to step s02 (CONT). If horizontal synchronization is obtained in steps s03 and s05, the process jumps to processing for changing the multiplier, etc., which is necessary during the synchronization period (JMP). When this process is finished, the process described above can be continued by returning to step sol. The determination output in step s02 can be determined, for example, by a flag obtained as a result of comparison by the arithmetic unit, and this can be used as the first condition code, and the synchronization signal can be used as the second condition code. In this way, by accessing one instruction once, multiple processing functions can be realized by using condition codes.

Next, for example, in the case of a Do/JMP/JMP command, the following condition and command relationship is established.

(1) When both condition codes Xi and X2 do not hold...D.

(2) When condition code X1 is established...
JMP (3) When condition code X2 is established...
JMP (4) When condition codes Xi and X2 are both established...JMP In this case, set the jump destination address to each (2).

If condition (3) is met, if you set different addresses, there will be 3 branches (
One is obtained for the Do command). In the case of condition (4), one of the two jump destination addresses takes priority.

For example, assume that the instruction at address a is Do/JMP/JMP, the first jump destination is address 40, and the second jump destination is address 50, for example. At this time, the addresses Adl and Ad2 of the jump address table 201 are set to 41.
The address and address 51 are set. In the program table 600, a 40th address instruction and a 50th address instruction are stored in advance.

For example, while executing the DO instruction (own address loop) (explained in Figure 4), if condition code X1 is established (for example, in response to the flag of the arithmetic unit), the jump will be made to address 40 as explained in Figure 5. and condition code x
When 2 is established (synchronization signal arrives), it jumps to address 50. This is effective, for example, when generating an address in synchronization with a synchronization signal and also generating an address for a video signal. For example, in order to generate an address for obtaining a triangular wave from the initial value to the maximum (MAX) as shown in FIG. 7(a), processing as shown in FIG. 7(b) is required.

That is, an initial value is given to obtain an initial address (step sl). Next, the increment is added to the initial address (step s2), and a comparator determines whether the value PA exceeds the maximum value (?, step s3). If the maximum value has not been reached, determine whether Kodaira synchronization has arrived (
Step s4). If the horizontal synchronization has arrived, the process branches to step s7, and if it has not arrived, the process branches to step 52IX.
D 77 f A. 1TnJbuM) T rA6'j
lt7'j If there is a 1m guard, PA- in step S5.
0 and determine whether horizontal synchronization has arrived (
Step s6). If horizontal synchronization has not arrived, the process returns to step s1. When horizontal synchronization occurs, the process branches to step S7. By performing such processing, it is possible to generate video signal addresses that change with various triangular waves as shown in FIG. 2(a).

Step s2. s3. s5. The loop of s6 corresponds to a DO command, and when horizontal synchronization occurs in step S4 or S6, condition 1 (first JMp@Q) is set to [, :2L
, XT17niikrnSTFFMPiJ does not exist, this corresponds to condition 2 (second JMP&order).

When the address waveform shown in figure (a) is generated continuously,
When horizontal synchronization has arrived, the program at the first jump destination may perform processing such as data rewriting or calculation required during the synchronization signal period, and then return to step S1. In the same figure (a), the address waveform is horizontally synchronized and phase synchronized.
=h h fsl 4 However, such a waveform can be obtained by changing the initial value in step s1 and the reference value (PA) in step S2.

Next, an example of a video signal processing system using the above-described sequencer will be described.

In FIG. 8, two 17-bit external video signals Al and Bl can be input to the network section 20. In addition to this, 17-bit input sections are prepared, making 32 in total.

The network unit 20 includes a plurality of units (for example, 17X't9?
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The eighth output section is grouped into two sets and each set is connected to the programmable arithmetic processing section 21 (Of>~21 (18)).Programmable arithmetic processing section 21 (01)
~21 Each output of (1B) is connected to the network section 2.
0, for example, the 17th to 32nd input sections. The network unit 20 is provided with an output unit to obtain a final video output. A plurality of output units (for example, from the first to the 16th) are provided, and can be connected to a similar network unit at the next stage.

A main control section 22 provides control signals to the network section 20 and the arithmetic processing sections 21 (01) to 21 (1B).

The input digital signal format handled by the above system is 17 bits in total, as shown in Figure (b), of which 1 bit is used as synchronization signal information, and the remaining bits are used as video signal data or synchronization signal. It is data. When the synchronization signal information is "1", the remaining 16 bits are synchronization signal data, and when it is "0", the remaining 16 bits are video signal data.

Further, the network section 20 has nine LSIs connected to one
The 17-bit input section and the 17-bit output section each have 2 bits assigned to each LSI. In this way, an increase in the number of terminals on one LSI is prevented. Further, the network section 20 has a built-in network control section, and the input/output connection system can be programmably switched by a command from the main control section 22 or the arithmetic processing section.

FIG. 9 shows one of the arithmetic processing units, for example 21 (01).

Depending on its control state, the network section 20 transmits the external video signals A1 and B to the arithmetic processing section 21 (01).
1 or other arithmetic processing sections can be supplied to this arithmetic processing section 21 (01) in pairs, or only one of the video signals can be supplied.

The arithmetic processing unit 21 (01) receives the video signal A2. It has two input sections that accept B2, and each input section is connected to a synchronization separation section 31A.
, 31B. Synchronization separation section 31A, 31B
The synchronization signal separated by is input to the sequencer 37,
It is used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), and the video signal A2. Used for time adjustment of B2.

The 16-bit video data separated by the synchronization separation sections 31A and 31B can be input to the multiplication section 32 and the calculation section 33. The multiplier 32 can multiply two video signals or can multiply one video signal by a constant or a variable value. The arithmetic unit 33 can add, subtract, or compare two video signals, add or subtract a certain value to one video signal, or perform a comparison process with a certain value.

The outputs obtained by the multiplier 32 and the arithmetic unit 33 can be further supplied to one input of each other, and
Also supplied.

The switching unit 34 selects and outputs one of the inputs, and the output thereof is derived via the synchronization adding unit 35. The synchronization adding section 35 can add or stop a synchronization signal.

This arithmetic processing section 21 (01) is further provided with a synchronization signal processing section 36 and an address generation section 38.

Furthermore, a control memory 41 is also included in addition to the external program memory. control memory 4
1 is a calculation processing unit 21 (01) When each data processing unit within the internal processing unit performs its own assigned processing, it is necessary to read out all instructions from the program memory each time. Programs can be stored in advance.

FIG. 10 shows an example of combining video signals using the above system. In this case, the network section 20 operates from the arithmetic processing section 21 (Of) to 21 (0
If the connection form of 3) is set as shown in the figure, the external video signal A
An output obtained by adding and combining 1 and 81 can be obtained. The video signal A1 is input to the multiplier of the arithmetic processing unit 21 (01) and multiplied by 6, and the video signal B1 is input to the multiplier of the arithmetic processing unit 21 (02).
) is input to the multiplier and multiplied by (1-α). The output of each multiplier is input to the arithmetic processing unit 21 (03), and is added and derived in the arithmetic unit. The network section 20 and the arithmetic processing sections 21 (01) to 21 (1B) can be switched to various forms depending on their processing purpose.

When each of the arithmetic processing units described above performs its own video signal processing, the sequencer described above is effectively used, and real-time processing of the video signal can be smoothly obtained when accessing instructions.

[Effects of the Invention] As described above, the present invention provides a circuit that is effective for real-time processing by requiring only one instruction for signals that require the same processing, such as pixels.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a further embodiment of the circuit in FIG. 1, and FIG.
5 to 5 are sequence explanatory diagrams shown to explain an example of the operation of this invention device, FIGS. 6 and 7 are explanatory diagrams showing an example of signal processing executed by this invention device, and FIG.
Figure (a) is an explanatory diagram showing the overall configuration of the device using this invention, Figure (b) is a diagram showing the signal format, Figure (c
) is a diagram shown to further explain the network section, FIG. 9 is a block diagram showing the configuration of the arithmetic processing section in FIG. 8, and FIG. 10 is an explanatory diagram showing an example of the signal processing form according to the present invention. . 100... External memory, 200... Address control section, 300... Multiplexer, 400... Instruction latch section, 500... Decoder section, 502... Clock control circuit. Applicant's representative Patent attorney Takehiko Suzue: ,,'>Figure 6 Horizontal syntax 7 units τ7 Figure X (1-α) Figure 10

Claims (1)

[Claims] an address control section that gives an address to the program memory; an instruction latch section that takes in program data from the program memory; and an instruction latch section that decodes the instruction latched in the instruction latch section and latches the instruction latch section according to the decoded contents. 1. A processor control device comprising: a decoder section that controls a control section that supplies a clock to the section and stops the clock.