JPH01236383A - Multiprocessor controller - Google Patents

Abstract

PURPOSE:To obtain a multiprocessor effective for real-time processing, in which the bit width of an instruction is not need to be extended, and instructions for respective arithmetic operation parts can be given without any delay by providing control memories to previously store respective primary instruction codes decoded by an instruction decoder in areas corresponding to respective data processing parts. CONSTITUTION:Program data read from a program memory 100 are supplied to an instruction decoder 200 in an LSI and decoded. The decoded instruction code is stored in a control memory 300. The control memory 300 has instruction code storing areas M1-Mn inherent in the respective processing parts correspondingly to plural data processing parts DP1-DPn in the LSI. Namely, the instructions of respective arithmetic processing parts (for example, a multiplication, an addition, a comparison, etc.,) are previously prepared for the control memory 300. Thus, prescribed processing can be obtained immediately by starting the data processing parts DP1-DPn by a flag, a synchronizing signal, etc., without accessing the program memory 100.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a multiprocessor control device that is effective when installed inside a digital video signal processing LSI used for real-time processing of video signals, for example. .

(Prior Art) Generally, a digital video signal processing system requires a plurality of calculation processes depending on the purpose of processing the video signal. Therefore, it is necessary to give instructions to each calculation unit individually, but if instructions are given from the program memory to each calculation unit via an instruction decoder depending on the processing time, there will not be enough time to obtain the required calculation result. Sometimes. Furthermore, in a video signal processing system, calculations for different purposes may be performed simultaneously in some cases. Therefore, if instructions are given to a plurality of arithmetic units at the same time, the bit width of the entire instruction must be increased, and the instruction area of the program memory must be expanded accordingly.

(Problems to be Solved by the Invention) As described above, in the video signal processing system, there are cases where a plurality of arithmetic units are operated simultaneously, and once a -degree command is given, the same command may be used thereafter. On the other hand, if the program memory is accessed only when the processing unit requests it, real-time processing may be inconvenient, and if the configuration is configured to give many instructions at the same time, the bit width must be increased. There is.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor control device that does not require expanding the bit width of instructions, can provide instructions to each calculation unit without delay, and is effective for real-time processing.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a program memory that stores a plurality of programs for a plurality of data processing units, and an instruction decoder that decodes instructions read from the program memory. The basic instruction code decoded by the instruction decoder is stored in advance in an area corresponding to each data processing section in order to omit accessing the program memory every time the processing of the plurality of data processing sections starts. The configuration includes a control memory that can store each instruction code.

(Function) With the above means, instructions for each arithmetic processing section (for example, multiplication, addition, comparison, etc.) are prepared in advance in the control memory, so instructions can be executed using flags or synchronization signals without accessing the program memory. By activating the data processing section, predetermined processing can be obtained immediately.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which 100 is a program memory, which is provided outside the LSI, for example, to facilitate expansion of program storage capacity. Program data read from the program memory 100 is supplied to an instruction decoder 200 inside the LSI and decoded.

The decoded instruction code is stored in the control memory 30.
Stored at 0. The control memory 300
Multiple data processing units D P (1) to D P inside the SI
Each processing unit has unique instruction code storage areas M(1) to M(n) corresponding to (n).

First, each data processing unit D P (1) to D P
(n) instruction code in each corresponding storage area M(1) to M
(n), for example, a program read address is given from a host computer to an address control section (not shown) provided inside the LSI via a register. As a result, program memory 1
Necessary program data is read from 00 and sequentially stored in each area of the control memory 300 through the instruction decoder 200.

This determines the processing to be handled by each data processing section within the LSI, and constructs the overall internal functions of the LSI, such as input video signal synthesis and gain control functions.

This embodiment is effective when performing video signal processing and when certain processing is often performed at a synchronization signal period. For example, when a burst signal arrives, it is extracted and color gain control data is calculated.

When the synchronization signal arrives, the real-time address of the video signal is returned to its initial value and incremented until the next synchronization signal arrives. Also, data (coefficients, etc.) is rewritten using the synchronization signal period. In such a case, if the program of each data processing unit is read from the memory by access each time, the access time will be insufficient and data will be lost.However, in this embodiment, for example, the synchronization signal itself is processed by data processing. By using this as a trigger for one data processing section or by using the flag of another data processing section, the next data processing section can be automatically operated without delay. Furthermore, since the instructions from the program memory 100 are stored in the control memory 300 in advance, there is no need to increase the bit width.

FIG. 2 is a block diagram of a digital video signal processing system using the present invention.
Two 7-bit external video signals AI and Bl can be input. In addition to this, 17-bit input sections are prepared, making 32 in total.

The network unit 20 includes a plurality of (for example, 48 systems) 17
It has a bit output section, and for example, the 17th to 48th output sections are grouped into two sets and each set is connected to the programmable arithmetic processing sections 21 (01) to 21 (113), respectively. Programmable calculation processing unit 21 (01) ~
Each output of 21 (113) is connected to the network section 2.
0, for example, the 17th to 32nd input sections. The network section 20 is provided with an output section for obtaining a final video output. A plurality of output units (for example, from the first to the 16th) are provided, and can be connected to a similar network unit at the next stage.

A main control section 22 provides control signals to the network section 20 and the arithmetic processing sections 21 (01) to 21 (1B).

The input digital signal format handled by the above system is 17 bits in total, as shown in Figure (b), of which 1 bit is used as synchronization signal information, and the remaining bits are used as video signal data or synchronization signal. It is data. When the synchronization signal information is "1", the remaining 16 bits are synchronization signal data, and when it is "0", the remaining 16 bits are video signal data.

Furthermore, the network section 20 includes, for example, nine LSIs or one
The 17-bit input section and output section each have 2 bits assigned to each LSI to facilitate wiring connection to one LSI. Further, the network section 20 has a built-in network control section, and the input/output connection system can be programmably switched by a command from the main control section 22 or the arithmetic processing section.

FIG. 3 shows one of the arithmetic processing units, for example 21 (Of).

Depending on its control state, the network section 20 transmits the external video signals A1 and B to the arithmetic processing section 21 (01).
1 or other arithmetic processing sections can be supplied to this arithmetic processing section 21 (Of) in pairs, or only one of the video signals can be supplied.

The arithmetic processing unit 21 (01) receives the video signal A2. It has two input sections that accept B2, and each input section is connected to a synchronization separation section 31A.
, 31B. Synchronization separation section 31A, 31B
The synchronization signal separated by is input to the sequencer 37,
It is used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), and the video signal A2. Used for time adjustment of B2.

The 16-bit video data separated by the synchronization separation sections 31A and 31B can be input to the multiplication section 32 and the calculation section 33. The multiplier 32 can multiply two video signals or can multiply one video signal by a constant or a variable value. The arithmetic unit 33 can add, subtract, or compare two video signals, add or subtract a certain value to one video signal, or perform a comparison process with a certain value.

The outputs obtained by the multiplier 32 and the arithmetic unit 33 can be further supplied to the human power of one of the two.
Also supplied.

The switching unit 34 selects and outputs one of the inputs, and the output thereof is derived via the synchronization adding unit 35. The synchronization adding section 35 can add or stop a synchronization signal.

This arithmetic processing section 21 (01) is further provided with a synchronization signal processing section 36 and an address generation section 38.

Furthermore, a control memory 41 is also included in addition to the external program memory. The control memory 41 is provided for each data processing section so that when each data processing section inside the arithmetic processing section 21 (01) performs its own assigned processing, there is no need to read out all instructions from the program memory each time. A unique program can be stored in advance.

FIG. 4 shows an example of combining video signals using the above system. In this case, the network unit 20 includes the arithmetic processing units 21 (Of) to 21 ([)
If the connection form of 3) is set as shown in the figure, the external video signal A
An output obtained by adding and combining 1 and 81 can be obtained. The video signal A1 is input to the multiplier of the arithmetic processing unit 21 (01) and multiplied by α, and the video signal B1 is input to the multiplier of the arithmetic processing unit 21 (02).
) is input to the multiplier and multiplied by (1-α). The output of each multiplier is input to the arithmetic processing unit 21 (03), and is added and derived in the arithmetic unit.

Network unit 20 and arithmetic processing unit 21 (01) to 2
1 (1B) can be switched to various forms depending on the processing purpose.

FIG. 5 shows in block form the processing functions that can be realized by further combining the systems shown in FIG. In this example, a processing unit 401 separates one composite video signal into luminance and color, and the output color signal and luminance signal are matrixed in the next processing unit 402 to derive R, G, and B signals.

Then, the RlG and B signals are subjected to γ correction in the processing section 403, and the resulting R, G and B signals are subjected to inverse matrix processing. Furthermore, by encoding the luminance signal and color signal obtained in this manner in the processing section 406, a matching video signal output is obtained.

[Effects of the Invention] As explained above, the present invention has multiple data processing units like the system shown in Figure 3, and has unique functions such as synchronous signal processing, address generation, and multiplication, addition and subtraction. It is effective when installed inside an LSI that performs data processing,
There is no need to expand the bit width of instructions, and instructions can be given to each arithmetic unit without delay, making it effective for real-time processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2(a) is a configuration explanatory diagram showing an example of a video signal processing system using the present invention, and FIG. 2(b) is a diagram showing a signal format. 3(C) is a diagram shown to further explain the network section, FIG. 3 is a block diagram showing the configuration of the arithmetic processing section of FIG. 2, and FIG. The explanatory diagram shown in FIG. 5 is a diagram showing an example of constructing a video signal processing system using the system shown in FIG. 2. 100...Program memory, 200...Mayray decoder, 300.41...Control memory, D
P (1) ~D P (n) --- Data processing section. Applicant's agent Patent attorney Takehiko Suzue Figure 2 17bit (b)

Claims (1)

[Claims] It includes a plurality of data processing units, a program memory that stores programs for each data processing unit, an instruction decoder that decodes instructions read from the program memory, and stores basic instruction codes decoded by the instruction decoder. , a control capable of storing instruction codes of the respective data processing units in areas corresponding to the plurality of data processing units, in order to omit accessing the program memory each time processing of the plurality of data processing units starts; A multiprocessor control device characterized by comprising a memory.