JPS5987547A - Microaddress extending system - Google Patents

Abstract

PURPOSE:To execute optionally an extension of a microaddress by providing a bit for designating an extension of the microaddress on a sub-control part, and branching to the extended microaddress when this bit is detected. CONSTITUTION:An output of a microaddress register 5 is inputted to control storage devices 24, 25. An output of the device 24 is held by a micro-instruction register 7, and is updated by a control of a micro-instruction updating circuit 6. At the same time, an output of the device 25 is held by a micro-instruction register 9, and is updated by a control of a micro-instruction updating circuit 8. The register 9 contains a microaddress extending bit 10, and its output is connected to a detecting circuit 11 and controls a microaddress extending circuit 4. The circuit 4 is made to branch to an address of the device 25 by an output of the circuit 11, a branch test of a micro-instruction and a result of a test designated by a field. In this way, by providing the extended bit 10, the microaddress can be extended optionally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microaddress expansion system, and is particularly directed to a system that can expand microaddresses without changing existing hardware.

[Prior art]

Conventionally, in microprogram-controlled data processing devices, the microaddress space has been expanded by adding a separate small-capacity control storage device and control unit without making any changes to the existing hardware. It is being said. That is, as shown in FIG. 1(a), the program in the control memory of the main controller 1 is initially executed in exactly the same way as the well-known method of branching to another address in the control memory. When the address (a) is reached, the process branches to the address (b) in the control storage device of the sub-control unit 2. The branched result is the sequence of sub-control unit 2 ``?0
Executes up to address (c) under the control of the controller.

Once the result of the calculation etc. is obtained, control is transferred to the main control unit 1 and returned to the branch source address (), and each step up to the address (e) is executed again under the sequence controller of the main control unit 1. Mike is executing four commands.

However, there are usually only a few steps in the instructions.

Some programs are executed using cropped quadratures, and although it is desired to increase the operation speed by reducing the number of steps even by one step, the method shown in FIG.
It takes 1 to 2 steps to branch to (b), and it takes 1 to 2 steps ζC to return to () to the address of the main control unit l, resulting in a decrease in operating speed.

Therefore, as a method for preventing the decrease in operating speed, a method has been proposed in which the main and sub-controllers 1 and 2 share a micro sequencer to perform parallel processing, as shown in FIG. 1(b). In other words, the address branched from the address (a) of the main control unit 1 to the address (b) of the sub-control unit 2 is changed to the address (b) of the sub-control unit 2 by the control of the shared microsequencer.
At the same time, the main controller 1 also advances steps from address (A) to address (H). In addition, there are no unnecessary steps when branching and returning, and the process can be executed with a smaller number of steps than the method shown in FIG. 1(a).

Note that even when two or more sub-control units 2 are added, control can be performed in exactly the same way.

However, the microinstructions stored in control storage
Divided into a main control section 1 and one or more sub-control sections 2, control sections 1, 2
In a method in which the micro-sequencers are shared and parallel processing is performed, when the micro-capacity increases when an additional mechanism is connected, and processing becomes impossible within the micro-address range of the main controller 1, the main controller is Since it was necessary to change the hardware such as increasing the bit length of the micro address of the control unit l, when connecting the additional mechanism, it was necessary to change the hardware of the processing unit that was the original design source, or to change the micro address within the range allowed by the micro address. This requires program design, etc., which is a drawback in the design of the processing device associated with the connection of additional mechanisms.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve these drawbacks by providing a system in which microinstructions are divided into a main controller and one or more subcontrollers, and each controller shares a microsequencer to perform parallel processing. An object of the present invention is to provide a microaddress expansion method capable of expanding microaddresses without changing existing hardware when connecting an additional mechanism of a sub-control unit to a processing device of a control unit.

(Summary of the Invention) The microaddress expansion method of the present invention is a data processing device using a microprogram control method in which microinstructions are stored in each control storage device of a main control section and a sub-control section, and each control section is processed in parallel. The sub-control unit is provided with a bit for instructing expansion of the microaddress, and when the instruction bit is detected, the subcontroller branches to the expanded microaddress.

[Embodiments of the invention] FIG. 2 is a diagram showing the operating principle of the present invention.

As shown in Fig. 1(b), the word length of the microinstruction is expanded only in a specific address range of the main control unit 1). Let us consider a case where the micro address of the control unit 1 is no longer compatible. In the embodiment of the present invention, without making any particular hardware changes, the microaddress is extended on the sub-control unit 2 side of the additional mechanism, and at the same time the main address corresponding to the extended address part 2' is Address part 1 of control unit 1
′ is apparently extended. - For example, if the address of the lO pit supports a memory capacity of 2, then
Assuming that only IK can be used in
If you want to increase K to 2K, add 1 bit to make an 11-bit address, and you can access 4 memory capacities. However, since the 10-bit length of the address cannot be changed, before branching, one unused bit in the microinstruction register of the subcontrol unit 2 is used to specify addresses 1 to 2 and addresses 2 to 4. It is changed to .

With this function, it is possible to branch from the address (?) of the main control unit 1 in FIG. ), and after executing to the extended address (m), restore 1 bit in the 5 microinstruction register to the original state.
It is possible to return to the address of the main control unit 1 ←). Apparently, the address (su) of the sub-control unit 2 returns to the extended address (k) of the main control unit 1, so the address portion 1' of the main control unit 1 has also been expanded.

FIG. 3 is a comparison diagram showing the address length of the present invention.

My main control unit 1 installed in an existing processing device.

Assuming that the clock address length is A and the word length stored in the control storage device of the main control unit 1 is C, FIG. 3(a) shows the capacity of the control storage device before the additional mechanism is connected.

Next, in FIG. 3(b), there is a
When connecting an additional mechanism, by having a subcontrol unit 2 that can be executed with the same microinstruction as the main control unit 1, the maximum microaddress length of the existing processing device is A, but the maximum microaddress length shown in B is It is possible to expand only
In addition, the hardware of the existing processing device is not changed. FIG. 4 is a block diagram of a data processing device showing an embodiment of the present invention.

In FIG. 4, 1 is a main control section, 2 is a sub-control section 1.3 is a micro address update circuit, and 4 is a micro.

address extension circuit, 5 is a microaddress register;
6 and 8 are microinstruction update circuits, 7.9 is a microinstruction register, 10 is a microaddress extension instruction bit, 11 is a detection circuit, 24 is a control storage device for the main control unit l,
25 is a control storage device of the sub-control unit 2;

The microaddress register δ is a register that holds the address of the microinstruction to be read next, and its output is stored in the control storage device 24.2 of the main control unit 1 and subcontrol unit 2.
Connected to 5. micro.

The output of the control storage device 24 is stored in the instruction register 7 and updated under the control of the microinstruction update circuit 6. Similarly, the microinstruction register 9 holds the output of the control storage device 25 and is updated under the control of the microinstruction update circuit 8. The microinstruction register 9 includes a microaddress extension bit IQ, the output of which is connected to the detection circuit 11 to control the microaddress extension circuit 4. or,
The microaddress register 5 is updated by the microaddress update circuit 3.

Note that the microaddress extension circuit 4 is actually a conditional branch control circuit, which performs microinstruction branch testing and
Based on the test result specified by the field and the output from the detection circuit 11, the control storage device 25 of the subcontroller 2
Branch to the address of .

FIG. 5 is a diagram illustrating the operation of FIG. 4.

The non-expanded micro address of the main controller l is 0-N
Suppose that Step 1: Micro address is N-n
-1, the main control unit 1 is 12. The sub-control unit 2 executes 13 microinstructions.

Step 2: If the micro address is N-n, then 1.1
The sub-control unit 2 executes the microinstruction 15 of El.

However, the micro address extension instruction pin in this El.

)10 is enabled (on), the micro address is.

It becomes possible to access a value of N or more, and in the next microinstruction step, according to the microinstruction 14 of the main control unit l that performs sequence control, an extended microaddress of M exceeding N, which is the maximum microaddress of the existing financial resource processing device 5, is accessed. can be executed.

That is, when the value of the microaddress extension instruction bit 10 in the microinstruction register 9 in FIG. When (N+1
) can branch to a larger address.

Step 3: If the microaddress is M11, the sub-control unit 2 executes the microinstruction 21 of E2.
By setting the microaddress extension instruction bit 10 in the microaddress to OFF, it becomes possible to access values of N or less from the extended microaddress, and in the next microinstruction step, the main control unit 1 that performs sequence control According to microinstruction 20, microaddress N-m can be executed.

That is, a part of the macro instruction register 7.9 contains the following information:
There is a 75 yield that specifies the address of the next microinstruction, and in microinstruction 14, that my.

- field is M, and in microinstruction 20, its field is (■ -m).

By providing the microaddress extension instruction bit IO in the sub-control unit 2 in this manner, any microaddress can be executed in the next microphone mouth command step.

[Effects of the Invention] As explained above, according to the present invention, when an additional mechanism is connected to an existing processing device, there is no need to change the existing hardware, and the micro-capacity can be adjusted arbitrarily to accommodate an increase in micro-capacity. Address expansion is possible.

[Brief explanation of the drawing]

Figure 1 shows the conventional microaddress extension method. 2 and 3 are explanatory diagrams showing the principle of the present invention, FIG. 4 is a block diagram of a data processing device showing an embodiment of the present invention, and FIG. 5 explains the operation of FIG. 4. This is a diagram. Main control section, 2: Sub-control section, 3: Micro address update circuit, Key micro address extension circuit, 5 = Micro address register, 6.8: Micro instruction update circuit, 71
9' Microinstruction register, 10: Microaddress extension instruction bit, 11: Detection circuit, 24, 2.5: Control storage device, A: Maximum microaddress length of existing financial resource processing device, B: Extended microaddress length. Patent applicant: Hitachi Co., Ltd. Fragment 1 Figure fa) Figure 2
1 ■ 3 Figure 4 Figure 52 - 5 7 N -n-1 Roni = = N 12 N-n 口 14 N-n-1-1 Ro = 2 16 M Ro ■ = = 118 M+1 [Eyoyo==]~2ON -m
mouth] 22 [=G13 <15 [G17 0=F19 [Ko[G21 [ll]23

Claims (1)

[Claims] In a microprogram control data processing device in which microcommands stored in respective control storage devices of a main control unit and a subcontrol unit are read respectively, and each control unit performs parallel processing,
A microaddress extension method characterized in that the sub-control unit is provided with a bit for instructing extension of a microaddress, and when it is detected that the extension instructing bit is a predetermined bit, a branch is made to the extended microaddress.