JPS56166530A - Bus controlling circuit for information processor - Google Patents

Bus controlling circuit for information processor

Info

Publication number
JPS56166530A
JPS56166530A JP6993380A JP6993380A JPS56166530A JP S56166530 A JPS56166530 A JP S56166530A JP 6993380 A JP6993380 A JP 6993380A JP 6993380 A JP6993380 A JP 6993380A JP S56166530 A JPS56166530 A JP S56166530A
Authority
JP
Japan
Prior art keywords
bus
outputted
clk
information
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6993380A
Other languages
Japanese (ja)
Inventor
Hiroshi Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6993380A priority Critical patent/JPS56166530A/en
Publication of JPS56166530A publication Critical patent/JPS56166530A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To reduce the effect of delay of information propagation on internal buses, by providing an internal bus output timing of a register information to the front edge of a basic clock and providing transfer gates to the input terminal of an external bus driver. CONSTITUTION:At the front edge where a basic clock CLK is 1, a readout control signal PSEL1 from an R/SFF11 is 1, the content of an address register AR1 is outputted to an internal bus 5 and an enable signal PENABLE is also 1 at the sae time. While the CLK is 1, tansfer gates 13, 14 are turned off and data on a bus 5 and the signal PENABLE are not transmitted to an external bus driver 7. The gates 13, 14 are turned on at the tail edge where the CLK is 0 and the address information and the enable signal ENABLE are outputted to an external bus 8 via the driver 7. Next, when the CLK is 1, a signal PSEL2 is outputted from an S/RFF12 at the front edge, the information of a data register 2 is outputted to the bus 5, and the data information and the signal ENABLE are outputted to the bus 8 at the tail edge where the CLK is 0.
JP6993380A 1980-05-26 1980-05-26 Bus controlling circuit for information processor Pending JPS56166530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6993380A JPS56166530A (en) 1980-05-26 1980-05-26 Bus controlling circuit for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6993380A JPS56166530A (en) 1980-05-26 1980-05-26 Bus controlling circuit for information processor

Publications (1)

Publication Number Publication Date
JPS56166530A true JPS56166530A (en) 1981-12-21

Family

ID=13416958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6993380A Pending JPS56166530A (en) 1980-05-26 1980-05-26 Bus controlling circuit for information processor

Country Status (1)

Country Link
JP (1) JPS56166530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2553542A1 (en) * 1983-10-14 1985-04-19 Hitachi Ltd Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2553542A1 (en) * 1983-10-14 1985-04-19 Hitachi Ltd Semiconductor integrated circuit

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