JPS56165460A - Facsimile device - Google Patents

Facsimile device

Info

Publication number
JPS56165460A
JPS56165460A JP6889280A JP6889280A JPS56165460A JP S56165460 A JPS56165460 A JP S56165460A JP 6889280 A JP6889280 A JP 6889280A JP 6889280 A JP6889280 A JP 6889280A JP S56165460 A JPS56165460 A JP S56165460A
Authority
JP
Japan
Prior art keywords
circuit
read
supplied
read data
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6889280A
Other languages
Japanese (ja)
Inventor
Takashi Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6889280A priority Critical patent/JPS56165460A/en
Publication of JPS56165460A publication Critical patent/JPS56165460A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof

Abstract

PURPOSE:To realize a high-speed operation of a facsimile device, by accumulating the read data into a memory in correspondence to the read line and transferring the accumulated data en bloc to a control part with every read line. CONSTITUTION:The read clock to be transmitted to a sensor 42 from a reading circuit 41 is supplied to a series-parallel converting circuit 51 as well as a counter 52. The circuit 51 fetches in parallel the read data of a prescribed number of bits and then converts it; and the counter 52 performs a count-up to a prescribed number to deliver a carry signal. This carry signal is supplied to either one of two systems of memories 54A and 54B through a control signal switch circuit 53 in the form of a write pulse. Thus the parallel read data sent from the circuit 51 is written into the memory 54A or 54B through a data switch circuit 55A or 55B. The carry signal is also supplied to an address counter 57, and the address to store the read data is designated.
JP6889280A 1980-05-26 1980-05-26 Facsimile device Pending JPS56165460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6889280A JPS56165460A (en) 1980-05-26 1980-05-26 Facsimile device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6889280A JPS56165460A (en) 1980-05-26 1980-05-26 Facsimile device

Publications (1)

Publication Number Publication Date
JPS56165460A true JPS56165460A (en) 1981-12-19

Family

ID=13386754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6889280A Pending JPS56165460A (en) 1980-05-26 1980-05-26 Facsimile device

Country Status (1)

Country Link
JP (1) JPS56165460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017169186A (en) * 2016-03-14 2017-09-21 株式会社リコー Image processing apparatus, information processing apparatus, image processing system, and image processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017169186A (en) * 2016-03-14 2017-09-21 株式会社リコー Image processing apparatus, information processing apparatus, image processing system, and image processing method

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