JPS56164625A - Phase shifting circuit - Google Patents

Phase shifting circuit

Info

Publication number
JPS56164625A
JPS56164625A JP6810080A JP6810080A JPS56164625A JP S56164625 A JPS56164625 A JP S56164625A JP 6810080 A JP6810080 A JP 6810080A JP 6810080 A JP6810080 A JP 6810080A JP S56164625 A JPS56164625 A JP S56164625A
Authority
JP
Japan
Prior art keywords
circuit
frequency
slave type
phase shifting
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6810080A
Other languages
Japanese (ja)
Inventor
Makoto Onga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6810080A priority Critical patent/JPS56164625A/en
Publication of JPS56164625A publication Critical patent/JPS56164625A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the constitution of an output signal having at least two types of phases, by constituting a 1/2 frequency divider with a master slave type FF circuit and supplying the output of an FF circuit for slaves and control pulses to a logical circuit.
CONSTITUTION: In a master slave type FF circuit 10, a clock signal CP is divided to 1/2 frequency, and frequency-divided outputs S1, -S1, are obtained from an FF circuit 10M for a master and this is fed to a color encoder 20 as the reference signal. On the other hand, from a slave type FF circuit 10S, frequency-dividing outputs S2, -S2 in which the same frequency-dividing ratio is obtained and the phase only is shifted by 90°, are outputted. In this case, the phase shifting amount changes with the duty of the clock signal CP, and when the duty is 50%, phase lag or lead is made to the signals S1, -S2 by 90 degrees.
COPYRIGHT: (C)1981,JPO&Japio
JP6810080A 1980-05-22 1980-05-22 Phase shifting circuit Pending JPS56164625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6810080A JPS56164625A (en) 1980-05-22 1980-05-22 Phase shifting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6810080A JPS56164625A (en) 1980-05-22 1980-05-22 Phase shifting circuit

Publications (1)

Publication Number Publication Date
JPS56164625A true JPS56164625A (en) 1981-12-17

Family

ID=13363976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6810080A Pending JPS56164625A (en) 1980-05-22 1980-05-22 Phase shifting circuit

Country Status (1)

Country Link
JP (1) JPS56164625A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0349715A2 (en) * 1988-07-06 1990-01-10 ANT Nachrichtentechnik GmbH Method and circuit for producing a phase-delayed clock signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0349715A2 (en) * 1988-07-06 1990-01-10 ANT Nachrichtentechnik GmbH Method and circuit for producing a phase-delayed clock signal

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