JPS56164447A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS56164447A
JPS56164447A JP6598680A JP6598680A JPS56164447A JP S56164447 A JPS56164447 A JP S56164447A JP 6598680 A JP6598680 A JP 6598680A JP 6598680 A JP6598680 A JP 6598680A JP S56164447 A JPS56164447 A JP S56164447A
Authority
JP
Japan
Prior art keywords
register
content
shifter
index
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6598680A
Other languages
Japanese (ja)
Inventor
Yoichi Kawabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP6598680A priority Critical patent/JPS56164447A/en
Publication of JPS56164447A publication Critical patent/JPS56164447A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To increase the processing speed accompained by accessing, by reading data through taking the sum of the value shifting the content of an index register by the number of bits designated and a prescribed variable as the address. CONSTITUTION:In an index mode, at first an index register designation section R1 designates a register Rj in a register group 1. The content of the register Rj is fed to a shifter 2. This content is shifted in the shifter 2 by the number indicated at a shift designation section S in the instruction. The output of the shifter 2 is added to the content of a displacement section D at an adder 3. This output is transferred to a memory address register and accessed to a prescribed memory. Efficient processing can be made for processing picking up elements in matrix, etc.
JP6598680A 1980-05-20 1980-05-20 Data processing device Pending JPS56164447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6598680A JPS56164447A (en) 1980-05-20 1980-05-20 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6598680A JPS56164447A (en) 1980-05-20 1980-05-20 Data processing device

Publications (1)

Publication Number Publication Date
JPS56164447A true JPS56164447A (en) 1981-12-17

Family

ID=13302838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6598680A Pending JPS56164447A (en) 1980-05-20 1980-05-20 Data processing device

Country Status (1)

Country Link
JP (1) JPS56164447A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829248A (en) * 1981-08-12 1983-02-21 Nec Corp Communication controller
JPS61165148A (en) * 1984-12-14 1986-07-25 Fujitsu Ltd Table access instructing system
JPH03248240A (en) * 1990-02-26 1991-11-06 Nec Corp Microcomputer
US6189086B1 (en) 1996-08-07 2001-02-13 Ricoh Company Ltd. Data processing apparatus
JP2011503758A (en) * 2007-11-20 2011-01-27 クゥアルコム・インコーポレイテッド System and method for determining the address of an element in a table

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829248A (en) * 1981-08-12 1983-02-21 Nec Corp Communication controller
JPS61165148A (en) * 1984-12-14 1986-07-25 Fujitsu Ltd Table access instructing system
JPH03248240A (en) * 1990-02-26 1991-11-06 Nec Corp Microcomputer
US6189086B1 (en) 1996-08-07 2001-02-13 Ricoh Company Ltd. Data processing apparatus
JP2011503758A (en) * 2007-11-20 2011-01-27 クゥアルコム・インコーポレイテッド System and method for determining the address of an element in a table

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