JPS5616252A - Tracer for logical operation - Google Patents

Abstract

PURPOSE: To obtain the effective log information of the hardware independently of the failure at an arbitrary period, by decoding the specific instruction of program and controlling the write-in and readout operation of the memory unit according to the decoded result.

CONSTITUTION: When the start instruction of logical operation tracing is made to the information processor 1, the instruction is decoded with the instruction decoder 2, the decoder 2 adds the decode signal 2a to the control section 3, the control section 3 gives the write-in permission signal 3a to the memory section 7 and the address counter 4 to instruct the write-in start. Based on this instruction, the content of the data register 6 is written in the memory section 7 and after that, the counter 4 is made +1. Further, the write-in operation is repeated every cycle until the stop condition is established from the unit 1 and the write-in stop signal 3b to the memory section 7 is made. Further, when the readout signal 3c is given to the counter 4 and the output gate 8, the trace information in the memory section 7 is sequentially read out and it is transferred to the output unit 9 via the output gate 8.

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