JPS56158472A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56158472A
JPS56158472A JP6428280A JP6428280A JPS56158472A JP S56158472 A JPS56158472 A JP S56158472A JP 6428280 A JP6428280 A JP 6428280A JP 6428280 A JP6428280 A JP 6428280A JP S56158472 A JPS56158472 A JP S56158472A
Authority
JP
Japan
Prior art keywords
layer
alpha rays
capacity
type
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6428280A
Other languages
Japanese (ja)
Inventor
Natsuo Tsubouchi
Shinichi Sato
Masahiko Denda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6428280A priority Critical patent/JPS56158472A/en
Publication of JPS56158472A publication Critical patent/JPS56158472A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain the MOSRAM device resistive to alpha rays by a method wherein the high density buried layer, having the homopolarity with a substrate, is provided at least on the lower part on either of a capacity section and a reverse conductive type diffusing region. CONSTITUTION:A P<+> layer 8 is implanted at the location where the cell capacity will be formed for a P type Si substrate 6, for example, and a P type epitaxial layer 7 is deposited on the whole surface. On this epitaxial layer 7, an FET is formed on a memory cell by providing the diffusion layer 5 to be used as a capacity electrode 2, a gate electrode 3 and a bit by means of a double-layer polycrystalline Si technique. Because of having the buried P<+> layer 8, the life of the electron generated by the alpha rays is shortened and as a result, no influence is inflicted on the capacity section. In like manner, a P type buried layer 8 is provided at the lower part of the N<+> diffusion layer 5 and the influence of the alpha rays on the bit line can be reduced. Through these procedures, the memory cell of the MOSRAM can be resistively formed to the alpha rays.
JP6428280A 1980-05-12 1980-05-12 Semiconductor device Pending JPS56158472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6428280A JPS56158472A (en) 1980-05-12 1980-05-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6428280A JPS56158472A (en) 1980-05-12 1980-05-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56158472A true JPS56158472A (en) 1981-12-07

Family

ID=13253713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6428280A Pending JPS56158472A (en) 1980-05-12 1980-05-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56158472A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62140458A (en) * 1985-12-13 1987-06-24 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPS62144352A (en) * 1985-12-18 1987-06-27 Mitsubishi Electric Corp Semiconductor integrated circuit device
US4688064A (en) * 1984-06-05 1987-08-18 Kabushiki Kaisha Toshiba Dynamic memory cell and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688064A (en) * 1984-06-05 1987-08-18 Kabushiki Kaisha Toshiba Dynamic memory cell and method for manufacturing the same
US4798794A (en) * 1984-06-05 1989-01-17 Kabushiki Kaisha Toshiba Method for manufacturing dynamic memory cell
JPS62140458A (en) * 1985-12-13 1987-06-24 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPS62144352A (en) * 1985-12-18 1987-06-27 Mitsubishi Electric Corp Semiconductor integrated circuit device

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