JPS56155451A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS56155451A
JPS56155451A JP5915980A JP5915980A JPS56155451A JP S56155451 A JPS56155451 A JP S56155451A JP 5915980 A JP5915980 A JP 5915980A JP 5915980 A JP5915980 A JP 5915980A JP S56155451 A JPS56155451 A JP S56155451A
Authority
JP
Japan
Prior art keywords
interruption
control device
input
output control
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5915980A
Other languages
Japanese (ja)
Other versions
JPS6319895B2 (en
Inventor
Toru Inosaki
Toshiyuki Maekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5915980A priority Critical patent/JPS56155451A/en
Publication of JPS56155451A publication Critical patent/JPS56155451A/en
Publication of JPS6319895B2 publication Critical patent/JPS6319895B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To remove restrictions on the using method of peripheral devices, by determining an interruption, which should be processed, by the instruction in the external control device of the peripheral control device when two or more interruptions occur in the interruption processing system. CONSTITUTION:If the interruption request occurs from input/output control device 18 on the line, where the interruption set release instruction in the program set by the operator is effective, during execution of this program, input/output control device 18 sets a flag in the internal RAM. Then, the program ignores this interruption to execute program instructions. When the program enters the line where the interruption set instruction is effective, the flag in input/output control device 18 is checked, and the interruption from input/output control device 18 is detected to execute the interruption processing. Consequently, since it is unnecessary that the main body side decides whether the interruption occurs from the computer user or the input/output control device, it is unnecessary to restrict the using method of connectable peripheral devices in the initial stage of the design of the computer main body.
JP5915980A 1980-04-30 1980-04-30 Electronic computer Granted JPS56155451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5915980A JPS56155451A (en) 1980-04-30 1980-04-30 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5915980A JPS56155451A (en) 1980-04-30 1980-04-30 Electronic computer

Publications (2)

Publication Number Publication Date
JPS56155451A true JPS56155451A (en) 1981-12-01
JPS6319895B2 JPS6319895B2 (en) 1988-04-25

Family

ID=13105300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5915980A Granted JPS56155451A (en) 1980-04-30 1980-04-30 Electronic computer

Country Status (1)

Country Link
JP (1) JPS56155451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62157953A (en) * 1985-12-28 1987-07-13 Honda Motor Co Ltd Microcomputer provided with abnormality detecting function
JPH01140739A (en) * 1987-11-27 1989-06-01 Fuji Electric Co Ltd Wafer centering and positioning apparatus of semiconductor wafer transfer equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518718A (en) * 1978-07-24 1980-02-09 Toshiba Corp Interruption system for specific program

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518718A (en) * 1978-07-24 1980-02-09 Toshiba Corp Interruption system for specific program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62157953A (en) * 1985-12-28 1987-07-13 Honda Motor Co Ltd Microcomputer provided with abnormality detecting function
JPH01140739A (en) * 1987-11-27 1989-06-01 Fuji Electric Co Ltd Wafer centering and positioning apparatus of semiconductor wafer transfer equipment
JPH0691151B2 (en) * 1987-11-27 1994-11-14 富士電機株式会社 Wafer centering positioning device for semiconductor wafer transfer equipment

Also Published As

Publication number Publication date
JPS6319895B2 (en) 1988-04-25

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