JPS5717047A - Processing system of interruption signal - Google Patents
Processing system of interruption signalInfo
- Publication number
- JPS5717047A JPS5717047A JP9156080A JP9156080A JPS5717047A JP S5717047 A JPS5717047 A JP S5717047A JP 9156080 A JP9156080 A JP 9156080A JP 9156080 A JP9156080 A JP 9156080A JP S5717047 A JPS5717047 A JP S5717047A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- delivered
- signal
- processor
- ack01
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To ensure an easy change for the sequence of interruption of the fixed input/output control device, by adding a simple FF circuit. CONSTITUTION:Interruption storage FFs 14 and 24 are set to input/output control devices 10 and 20, respectively, and at the same time an interruption process requesting signal ATN0 is delivered to an arithmetic processor 1 from the devices 10 and 20 each in case a priority FF25 is set at the device 20. On the other hand, the interruption acknowledgement signal ACK01 is delivered to the device 10 from the processor 1. Then the acknowledgement signal ACK02 is delivered to the device 20 from an interruption gate circuit 11 via a signal amplifier 13, and interruption processing is carried out at the device 20. After this, the signal ACK01 is delivered to the device 10 from the processor 1, and an interruption acknowledgement signal ANS01 is delivered from the device 10 to carry out interruption processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9156080A JPS5717047A (en) | 1980-07-04 | 1980-07-04 | Processing system of interruption signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9156080A JPS5717047A (en) | 1980-07-04 | 1980-07-04 | Processing system of interruption signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5717047A true JPS5717047A (en) | 1982-01-28 |
Family
ID=14029887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9156080A Pending JPS5717047A (en) | 1980-07-04 | 1980-07-04 | Processing system of interruption signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5717047A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5172244A (en) * | 1974-12-20 | 1976-06-22 | Hitachi Ltd |
-
1980
- 1980-07-04 JP JP9156080A patent/JPS5717047A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5172244A (en) * | 1974-12-20 | 1976-06-22 | Hitachi Ltd |
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