JPS569845A - Interruption mask control system - Google Patents

Interruption mask control system

Info

Publication number
JPS569845A
JPS569845A JP8400979A JP8400979A JPS569845A JP S569845 A JPS569845 A JP S569845A JP 8400979 A JP8400979 A JP 8400979A JP 8400979 A JP8400979 A JP 8400979A JP S569845 A JPS569845 A JP S569845A
Authority
JP
Japan
Prior art keywords
mask
interruption
job
processing
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8400979A
Other languages
Japanese (ja)
Other versions
JPS5756748B2 (en
Inventor
Toshio Asaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8400979A priority Critical patent/JPS569845A/en
Publication of JPS569845A publication Critical patent/JPS569845A/en
Publication of JPS5756748B2 publication Critical patent/JPS5756748B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to exercise mask control without providing a processor with dedicated instructions for on-off control over an interruption mask, by using two masks.
CONSTITUTION: Input-output controllers 2-1W2-n are provided with two masks A(4-1W4-n) and B(5-1W5-n). Microprocessor MPu1, when carrying out job (a) (executed by steps a1Waq) for input-output controller 3-1, carries out the job through mask A(4-1). To inhibit interruption processing such as processing (b) from another input-output unit 3-2 during the processing from step ap to step aq, mask-A-OFF and data are entered into the register provided to unit 2-1 from MPu1 in step ap and mask A is turned off, so that logic [0] will be generated at mask A. Therefore, even if an interruption request based upon job (b) is sent from unit 3-2 after step ap, this interrupt request signal is not transferred to interruption processing hardware.
COPYRIGHT: (C)1981,JPO&Japio
JP8400979A 1979-07-04 1979-07-04 Interruption mask control system Granted JPS569845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8400979A JPS569845A (en) 1979-07-04 1979-07-04 Interruption mask control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8400979A JPS569845A (en) 1979-07-04 1979-07-04 Interruption mask control system

Publications (2)

Publication Number Publication Date
JPS569845A true JPS569845A (en) 1981-01-31
JPS5756748B2 JPS5756748B2 (en) 1982-12-01

Family

ID=13818592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8400979A Granted JPS569845A (en) 1979-07-04 1979-07-04 Interruption mask control system

Country Status (1)

Country Link
JP (1) JPS569845A (en)

Also Published As

Publication number Publication date
JPS5756748B2 (en) 1982-12-01

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