JPS56153846A - Frequency dividing circuit - Google Patents

Frequency dividing circuit

Info

Publication number
JPS56153846A
JPS56153846A JP5739480A JP5739480A JPS56153846A JP S56153846 A JPS56153846 A JP S56153846A JP 5739480 A JP5739480 A JP 5739480A JP 5739480 A JP5739480 A JP 5739480A JP S56153846 A JPS56153846 A JP S56153846A
Authority
JP
Japan
Prior art keywords
phib
signal
level
clock signal
feedback circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5739480A
Other languages
Japanese (ja)
Other versions
JPS6242415B2 (en
Inventor
Fumiaki Tsukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5739480A priority Critical patent/JPS56153846A/en
Publication of JPS56153846A publication Critical patent/JPS56153846A/en
Publication of JPS6242415B2 publication Critical patent/JPS6242415B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/48Gating or clocking signals applied to all stages, i.e. synchronous counters with a base or radix other than a power of two
    • H03K23/483Gating or clocking signals applied to all stages, i.e. synchronous counters with a base or radix other than a power of two with a base which is an odd number
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/44Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors

Landscapes

  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make the operation high-speed and reduce power consumption, by making the phase of the clock signal, which is given to the load means in the feedback circuit of the ring counter type odd frequency divider, different from the phase of the clock signal which is given to the feedback input. CONSTITUTION:The 1/15 frequency dividing circuit consists of the 16-stage shift register, where the first transfer gates TFG whose gates clock signal phiA is connected to and the second transfer gates TFG whose gates clock signal phiB of a phase opposite to signal phiA is connected to are connected alternately with inverters IV interposed, and the feedback circuit to which outputs of the 13th stage synchronized with phiA, and the 14th stage and the 16th stage synchronized with phiB are inputted. Signal phiB is applied to the gate of load transistor TRT7' of the feedback circuit. When output A' of the feedback circuit changes from the L level to the H level, the output of IV14' changes from the H level to the L level, and load capacity Cl' is charged rapidly by signal phiB of TRT7' through TRT5' is turned off. When signal phiB is broken, capacity C1' is discharged rapidly because TRs T3 and T4 are low- resistance.
JP5739480A 1980-04-30 1980-04-30 Frequency dividing circuit Granted JPS56153846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5739480A JPS56153846A (en) 1980-04-30 1980-04-30 Frequency dividing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5739480A JPS56153846A (en) 1980-04-30 1980-04-30 Frequency dividing circuit

Publications (2)

Publication Number Publication Date
JPS56153846A true JPS56153846A (en) 1981-11-28
JPS6242415B2 JPS6242415B2 (en) 1987-09-08

Family

ID=13054399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5739480A Granted JPS56153846A (en) 1980-04-30 1980-04-30 Frequency dividing circuit

Country Status (1)

Country Link
JP (1) JPS56153846A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0512048A1 (en) * 1990-01-25 1992-11-11 David Sarnoff Research Center, Inc. High speed frequency divider circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424975Y2 (en) * 1987-04-02 1992-06-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0512048A1 (en) * 1990-01-25 1992-11-11 David Sarnoff Research Center, Inc. High speed frequency divider circuit
EP0512048A4 (en) * 1990-01-25 1994-02-16 David Sarnoff Research Center, Inc.

Also Published As

Publication number Publication date
JPS6242415B2 (en) 1987-09-08

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