GB1278373A - Input synchronizer circuit - Google Patents

Input synchronizer circuit

Info

Publication number
GB1278373A
GB1278373A GB3609970A GB3609970A GB1278373A GB 1278373 A GB1278373 A GB 1278373A GB 3609970 A GB3609970 A GB 3609970A GB 3609970 A GB3609970 A GB 3609970A GB 1278373 A GB1278373 A GB 1278373A
Authority
GB
United Kingdom
Prior art keywords
gate
output
input
low
nand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3609970A
Inventor
Gary Lee Heimbigner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
North American Rockwell Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by North American Rockwell Corp filed Critical North American Rockwell Corp
Publication of GB1278373A publication Critical patent/GB1278373A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback

Abstract

1278373 Logic and switching circuits NORTH AMERICAN ROCKWELL CORP 24 July 1970 [12 Dec 1969] 36099/70 Heading H3T In Fig. 1, NAND gates 2, 5 respond to an input at 3 when a clock pulse # 1 occurs, the output being held by a regenerative feedback loop 12 and gate 9 (e.g. OR gate) until the next clock pulse. When NAND gate 2 has both inputs high, input 6 to NAND gate 5 is low and so output 7 is high. The invertor 11 gives a low input to OR gate 9 therefore, so that when # 1 ends, the output of OR gate 9 goes low and output is maintained high. If input 3 goes low then NAND gate 2 output is high, and when # 1 again goes high to make OR gate output high then NAND gate 5 output low and the regenerative circuit 5, 11, 9 sets to the opposite state. The gates use F.E.T.s (Fig. 2, not shown); a series pair (21, 22) form gate 2, and another series pair (34, 38) from gate 5, the OR function being introduced by a F.E.T. (39) in parallel with F.E.T. (38). The invertor is another F.E.T. (49) and each gate 2, 5 and the invertor has a respective load F.E.T. (30, 45, 55).
GB3609970A 1969-12-12 1970-07-24 Input synchronizer circuit Expired GB1278373A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88452569A 1969-12-12 1969-12-12

Publications (1)

Publication Number Publication Date
GB1278373A true GB1278373A (en) 1972-06-21

Family

ID=25384824

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3609970A Expired GB1278373A (en) 1969-12-12 1970-07-24 Input synchronizer circuit

Country Status (4)

Country Link
JP (1) JPS5119736B1 (en)
DE (1) DE2037161A1 (en)
GB (1) GB1278373A (en)
NL (1) NL7012469A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4399377A (en) * 1979-01-23 1983-08-16 National Research Development Corporation Selectively operable bit-serial logic circuit
US5111480A (en) * 1987-09-28 1992-05-05 Siemens Aktiengesellschaft Method for equalization of the pulse widths of a digital signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4399377A (en) * 1979-01-23 1983-08-16 National Research Development Corporation Selectively operable bit-serial logic circuit
US5111480A (en) * 1987-09-28 1992-05-05 Siemens Aktiengesellschaft Method for equalization of the pulse widths of a digital signal

Also Published As

Publication number Publication date
JPS5119736B1 (en) 1976-06-19
NL7012469A (en) 1971-06-15
DE2037161A1 (en) 1971-06-16

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee