JPS56153816A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS56153816A
JPS56153816A JP5620780A JP5620780A JPS56153816A JP S56153816 A JPS56153816 A JP S56153816A JP 5620780 A JP5620780 A JP 5620780A JP 5620780 A JP5620780 A JP 5620780A JP S56153816 A JPS56153816 A JP S56153816A
Authority
JP
Japan
Prior art keywords
collectors
same time
dynamic range
resistances
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5620780A
Other languages
Japanese (ja)
Inventor
Tetsuo Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5620780A priority Critical patent/JPS56153816A/en
Publication of JPS56153816A publication Critical patent/JPS56153816A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
    • H03G11/002—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general without controlling loop

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain the broken-line type amplification characteristics that is obtained by combining plural different amplification characteristics within and outside a prescribed range and furthermore secure an optional setting of the characteristics as well as realize an application to formation of an IC, by installing at least two sets of differential ampilfiers having two transistors and different input dynamic ranges. CONSTITUTION:The emitters of transistors(TR) Q1 and Q2 are made common to each other via resistances R1 and R2 and at the same time grounded via the constant current circuit I1, and the collectors of Q1 and Q2 are connected to the power supply terminal VCC via lead resistances RL1 and RL2. Thus a differetial amplifier is formed with a prescribed dynamic range. At the same time, the emitters of TRs Q3 and Q4 are made common to each other via resistances R3 and R4 and also grounded via the constant current circuit I2, and the collectors are connected to the collectors of Q1 and Q2 respectively. Thus a differential amplifier is obtained with a dynamic range different from the above-mentioned dynamic range. The bases of TRs Q1 and Q3 plus Q2 and Q4 are connected in common, and at least one of these bases is used for an input terminal. At the same time, the collector of each TR is used for at least an output terminal.
JP5620780A 1980-04-30 1980-04-30 Signal processing circuit Pending JPS56153816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5620780A JPS56153816A (en) 1980-04-30 1980-04-30 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5620780A JPS56153816A (en) 1980-04-30 1980-04-30 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS56153816A true JPS56153816A (en) 1981-11-28

Family

ID=13020657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5620780A Pending JPS56153816A (en) 1980-04-30 1980-04-30 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS56153816A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127412A (en) * 1983-01-12 1984-07-23 Nec Corp Logarithmic compressing and amplifying circuit
JPS6066511A (en) * 1983-09-22 1985-04-16 Nec Corp Logarithmic compression amplifying circuit
JPS6223690A (en) * 1985-07-24 1987-01-31 Hitachi Micro Comput Eng Ltd Signal processing circuit
JPS6223606A (en) * 1985-07-24 1987-01-31 Fujitsu Ltd Compression amplifier
JPS63185315U (en) * 1987-05-22 1988-11-29
JPH0197612U (en) * 1987-12-22 1989-06-29

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127412A (en) * 1983-01-12 1984-07-23 Nec Corp Logarithmic compressing and amplifying circuit
JPS6066511A (en) * 1983-09-22 1985-04-16 Nec Corp Logarithmic compression amplifying circuit
JPS6223690A (en) * 1985-07-24 1987-01-31 Hitachi Micro Comput Eng Ltd Signal processing circuit
JPS6223606A (en) * 1985-07-24 1987-01-31 Fujitsu Ltd Compression amplifier
JPH055403B2 (en) * 1985-07-24 1993-01-22 Fujitsu Ltd
JPS63185315U (en) * 1987-05-22 1988-11-29
JPH0197612U (en) * 1987-12-22 1989-06-29
JPH0526814Y2 (en) * 1987-12-22 1993-07-07

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