JPS56143590A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make zero the power consumption of a CMOS semiconductor memory by controlling so that the power source current becomes minimum by a memory-chip nonselection signal regardless of an input signal level when the memory is unselected. CONSTITUTION:When the memory is unselected, namely, when selection signal CS' is held at the high level, the inverter circuit consisting of transistors(TR) Q15 and Q16 holds control signal phic at the low level. In signal input circuit 1, p channel TR Q13 is conducted and n channel Q14 is cut off. Therefore, coupling point P3 is held at the high level regardless of the voltage level of input signal A and the inverter circuit consisting of Q11 and Q12 holds output point P2 at the low level. The level at coupling point P3 is equal to that of power source voltage V and Q11 and Q14 are both cut off, so no power source current flows through signal input circuit 1, making the power consumption zero.