JPS56137638A - Dry etching method and its device - Google Patents

Dry etching method and its device

Info

Publication number
JPS56137638A
JPS56137638A JP4068280A JP4068280A JPS56137638A JP S56137638 A JPS56137638 A JP S56137638A JP 4068280 A JP4068280 A JP 4068280A JP 4068280 A JP4068280 A JP 4068280A JP S56137638 A JPS56137638 A JP S56137638A
Authority
JP
Japan
Prior art keywords
electrode
hole
plane
setting
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4068280A
Other languages
Japanese (ja)
Inventor
Masahiro Iiri
Fumio Fukino
Kosuke Oshio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4068280A priority Critical patent/JPS56137638A/en
Publication of JPS56137638A publication Critical patent/JPS56137638A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form a high-precision and microetched pattern by performing reactive ion etching and plasma etching continuously on the same device equipped with a parallel flat plate electrode. CONSTITUTION:Flat plate-shaped electrode 4 and electrode 5 are provided in parallel inside a chamber 1. One electrode, for instance, the electrode 5 is equipped with a through hole 8, in which a setting member 7 for an object to be etched 26 is installed. First, the electroconductive setting plane 10 of the setting member 7 is set in the through hole 8 in such manner that the said plane is on the same level as the electrode 5. Then a reactive etching is carried out to such extent that the exposed surface of a coat where a resist pattern is provided, partially remains in a film thickness direction. Following this procedure, an electroconductive auxiliary plate 11 connected and fixed to the setting plane 10 by means of an insulative barlike element 9, is set in the through hole 8 and the remaining coat is plasma-etched by arranging the setting plane 10 between electrodes in such manner that it is insulated. Under this constitution, it is possible to minimize undercuts or injuries on the base and thus form a microetched pattern with high precision.
JP4068280A 1980-03-29 1980-03-29 Dry etching method and its device Pending JPS56137638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4068280A JPS56137638A (en) 1980-03-29 1980-03-29 Dry etching method and its device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4068280A JPS56137638A (en) 1980-03-29 1980-03-29 Dry etching method and its device

Publications (1)

Publication Number Publication Date
JPS56137638A true JPS56137638A (en) 1981-10-27

Family

ID=12587300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4068280A Pending JPS56137638A (en) 1980-03-29 1980-03-29 Dry etching method and its device

Country Status (1)

Country Link
JP (1) JPS56137638A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0936106A (en) * 1996-08-22 1997-02-07 Hitachi Ltd Plasma treatment device
JP2010212028A (en) * 2009-03-09 2010-09-24 Epson Toyocom Corp Plasma treatment device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0936106A (en) * 1996-08-22 1997-02-07 Hitachi Ltd Plasma treatment device
JP2010212028A (en) * 2009-03-09 2010-09-24 Epson Toyocom Corp Plasma treatment device

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