JPS5613588A - Refreshing circuit for dynamic ram - Google Patents

Refreshing circuit for dynamic ram

Info

Publication number
JPS5613588A
JPS5613588A JP8776279A JP8776279A JPS5613588A JP S5613588 A JPS5613588 A JP S5613588A JP 8776279 A JP8776279 A JP 8776279A JP 8776279 A JP8776279 A JP 8776279A JP S5613588 A JPS5613588 A JP S5613588A
Authority
JP
Japan
Prior art keywords
memory
refreshment
electric power
frequency
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8776279A
Other languages
Japanese (ja)
Inventor
Shinobu Kameoka
Hidemasa Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8776279A priority Critical patent/JPS5613588A/en
Publication of JPS5613588A publication Critical patent/JPS5613588A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Abstract

PURPOSE:To back up a memory for a long period with small batteries in case of an electric power failure by improving the efficiency of utilization of the memory by allowing a refresh frequency to vary with ambient temperature. CONSTITUTION:With regard to the oscillator consisting of NAND circuit 1, capacitor 3, resistance 4, and thermistor 8, its output is a rectangular wave whose period is determined by 0.7RTC, providing that RT is the resistance value of thermistor 8 and C is the capacity of the capacitor. Its oscillation frequency is high at a high temperature and low at a low temperature. This rectangular wave is processed by memory clock generating circuit 5 to obtain a clock for refreshment is also converted into an address signal for refreshment by memory address generating circuit 6. With those clock and signal, the memory contents of dynamic RAM7 are refreshed. In this case, the frequency varies with ambient temperature and the memory operates with high efficiency of utilization. Here, when an element having electric power current, in refreshment, in proportion to the frequency is used as RAM7, miniature battery for backup current for a electric power failure can be used.
JP8776279A 1979-07-11 1979-07-11 Refreshing circuit for dynamic ram Pending JPS5613588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8776279A JPS5613588A (en) 1979-07-11 1979-07-11 Refreshing circuit for dynamic ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8776279A JPS5613588A (en) 1979-07-11 1979-07-11 Refreshing circuit for dynamic ram

Publications (1)

Publication Number Publication Date
JPS5613588A true JPS5613588A (en) 1981-02-09

Family

ID=13923953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8776279A Pending JPS5613588A (en) 1979-07-11 1979-07-11 Refreshing circuit for dynamic ram

Country Status (1)

Country Link
JP (1) JPS5613588A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225968A (en) * 1984-04-25 1985-11-11 Seiko Epson Corp Electronic computer
US4716551A (en) * 1983-09-14 1987-12-29 Nec Corporation Semiconductor memory device with variable self-refresh cycle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4716551A (en) * 1983-09-14 1987-12-29 Nec Corporation Semiconductor memory device with variable self-refresh cycle
JPS60225968A (en) * 1984-04-25 1985-11-11 Seiko Epson Corp Electronic computer

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