JPS56134862A - Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal - Google Patents

Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal

Info

Publication number
JPS56134862A
JPS56134862A JP3797380A JP3797380A JPS56134862A JP S56134862 A JPS56134862 A JP S56134862A JP 3797380 A JP3797380 A JP 3797380A JP 3797380 A JP3797380 A JP 3797380A JP S56134862 A JPS56134862 A JP S56134862A
Authority
JP
Japan
Prior art keywords
control circuit
frequency control
digital processing
multiple signal
processing type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3797380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6337987B2 (enExample
Inventor
Botaro Hirosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3797380A priority Critical patent/JPS56134862A/ja
Publication of JPS56134862A publication Critical patent/JPS56134862A/ja
Publication of JPS6337987B2 publication Critical patent/JPS6337987B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
JP3797380A 1980-03-25 1980-03-25 Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal Granted JPS56134862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3797380A JPS56134862A (en) 1980-03-25 1980-03-25 Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3797380A JPS56134862A (en) 1980-03-25 1980-03-25 Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal

Publications (2)

Publication Number Publication Date
JPS56134862A true JPS56134862A (en) 1981-10-21
JPS6337987B2 JPS6337987B2 (enExample) 1988-07-27

Family

ID=12512500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3797380A Granted JPS56134862A (en) 1980-03-25 1980-03-25 Pilot phase and frequency control circuit of digital processing type receiver for orthogonal multiple signal

Country Status (1)

Country Link
JP (1) JPS56134862A (enExample)

Also Published As

Publication number Publication date
JPS6337987B2 (enExample) 1988-07-27

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