JPS56133839A - Process for semiconductor substrate - Google Patents

Process for semiconductor substrate

Info

Publication number
JPS56133839A
JPS56133839A JP3713680A JP3713680A JPS56133839A JP S56133839 A JPS56133839 A JP S56133839A JP 3713680 A JP3713680 A JP 3713680A JP 3713680 A JP3713680 A JP 3713680A JP S56133839 A JPS56133839 A JP S56133839A
Authority
JP
Japan
Prior art keywords
substrate
diffusion layer
layer
reverse side
far
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3713680A
Other languages
Japanese (ja)
Other versions
JPS628018B2 (en
Inventor
Takashi Shimada
Yasuo Kano
Junichi Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3713680A priority Critical patent/JPS56133839A/en
Publication of JPS56133839A publication Critical patent/JPS56133839A/en
Publication of JPS628018B2 publication Critical patent/JPS628018B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To prevent a deterioration in crystallization of a surface accompanying with a gettering process by forming a blocking diffusion layer on the surface of a semiconductor substrate wherein the surface of the substrate is removed with the blocking diffusion layer as far as predetermined depth after diffusing P on the reverse side of the substrate. CONSTITUTION:A blocking diffusion layer 2 of SiO2 or the like is formed on the surface of an Si substrate 1 consisting of dislocationless CZ crystal doped B and P is diffused on the reverse side of the substrate with high concentration to form a P diffusion layer 3 and a P glass layer 4 respectively and the SiO2 film 2 on the surface of the substrate is removed after providing a CVD film 5 on the reverse side of the layer 4 to eliminate the surface region of the substrate as far as 10mu or more in depth (the position of a pointed chain line). In this way, occurrence of a stacked layer defect accompanying with a gettering process and the influence of P will be prevented. Therefore, the electrical characteristics of an Si device will be improved.
JP3713680A 1980-03-24 1980-03-24 Process for semiconductor substrate Granted JPS56133839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3713680A JPS56133839A (en) 1980-03-24 1980-03-24 Process for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3713680A JPS56133839A (en) 1980-03-24 1980-03-24 Process for semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS56133839A true JPS56133839A (en) 1981-10-20
JPS628018B2 JPS628018B2 (en) 1987-02-20

Family

ID=12489192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3713680A Granted JPS56133839A (en) 1980-03-24 1980-03-24 Process for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS56133839A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0229180A1 (en) * 1985-06-17 1987-07-22 Sony Corporation Process for manufacturing semiconductor devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0453850Y2 (en) * 1986-02-27 1992-12-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0229180A1 (en) * 1985-06-17 1987-07-22 Sony Corporation Process for manufacturing semiconductor devices

Also Published As

Publication number Publication date
JPS628018B2 (en) 1987-02-20

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