JPS56118396A - Method of forming conductive layer of circuit board - Google Patents

Method of forming conductive layer of circuit board

Info

Publication number
JPS56118396A
JPS56118396A JP2247180A JP2247180A JPS56118396A JP S56118396 A JPS56118396 A JP S56118396A JP 2247180 A JP2247180 A JP 2247180A JP 2247180 A JP2247180 A JP 2247180A JP S56118396 A JPS56118396 A JP S56118396A
Authority
JP
Japan
Prior art keywords
circuit board
conductive layer
forming conductive
forming
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2247180A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6155799B2 (cs
Inventor
Akihiro Koutani
Yasuhiko Hino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2247180A priority Critical patent/JPS56118396A/ja
Priority to FR8103559A priority patent/FR2476913B1/fr
Publication of JPS56118396A publication Critical patent/JPS56118396A/ja
Priority to US06/429,636 priority patent/US4434544A/en
Publication of JPS6155799B2 publication Critical patent/JPS6155799B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2247180A 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board Granted JPS56118396A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2247180A JPS56118396A (en) 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board
FR8103559A FR2476913B1 (fr) 1980-02-25 1981-02-23 Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit
US06/429,636 US4434544A (en) 1980-02-25 1982-09-30 Multilayer circuit and process for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2247180A JPS56118396A (en) 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board

Publications (2)

Publication Number Publication Date
JPS56118396A true JPS56118396A (en) 1981-09-17
JPS6155799B2 JPS6155799B2 (cs) 1986-11-29

Family

ID=12083616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2247180A Granted JPS56118396A (en) 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board

Country Status (1)

Country Link
JP (1) JPS56118396A (cs)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893297A (ja) * 1981-11-30 1983-06-02 日本電気株式会社 導体回路の形成方法
JPS58128797A (ja) * 1982-01-27 1983-08-01 日本電気株式会社 多層セラミツク基板の製造方法
JP2012089216A (ja) * 2010-10-22 2012-05-10 Dainippon Printing Co Ltd サスペンション用基板、サスペンション用基板の製造方法、サスペンション、素子付サスペンション、およびハードディスクドライブ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893297A (ja) * 1981-11-30 1983-06-02 日本電気株式会社 導体回路の形成方法
JPS58128797A (ja) * 1982-01-27 1983-08-01 日本電気株式会社 多層セラミツク基板の製造方法
JP2012089216A (ja) * 2010-10-22 2012-05-10 Dainippon Printing Co Ltd サスペンション用基板、サスペンション用基板の製造方法、サスペンション、素子付サスペンション、およびハードディスクドライブ

Also Published As

Publication number Publication date
JPS6155799B2 (cs) 1986-11-29

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