JPS56116156A - Circuit check system for information processor - Google Patents

Circuit check system for information processor

Info

Publication number
JPS56116156A
JPS56116156A JP1919880A JP1919880A JPS56116156A JP S56116156 A JPS56116156 A JP S56116156A JP 1919880 A JP1919880 A JP 1919880A JP 1919880 A JP1919880 A JP 1919880A JP S56116156 A JPS56116156 A JP S56116156A
Authority
JP
Japan
Prior art keywords
decoder
rom12
input
signal
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1919880A
Other languages
Japanese (ja)
Inventor
Akihiro Sueda
Masanori Kinugasa
Seiichi Hirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1919880A priority Critical patent/JPS56116156A/en
Publication of JPS56116156A publication Critical patent/JPS56116156A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To reduce a test time, by rejecting the duplicated steps of a software check by program logic array. CONSTITUTION:The software is assembled by writing in instructions in ROM12. The address decoder 13 is connected to the rows of ROM12 and the information 14 from the counter 18 is input to the address decoder 13. Further, the column decoder 15 is connected to the column lines of ROM12. The latch 16 is connected to the column decoder 15 and the instruction decoder 17 is connected to the latch output. Further, the control circuit 19 is connected to the counter 18 and the input circuit 20 and various data signals are connected to the control circuit 19. To the input circuit 20, the input signal RCH from the check terminal 21, jump signal JP from the instruction decoder 17, subroutine call signal SC and subroutine return signal SR are fed.
JP1919880A 1980-02-20 1980-02-20 Circuit check system for information processor Pending JPS56116156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1919880A JPS56116156A (en) 1980-02-20 1980-02-20 Circuit check system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1919880A JPS56116156A (en) 1980-02-20 1980-02-20 Circuit check system for information processor

Publications (1)

Publication Number Publication Date
JPS56116156A true JPS56116156A (en) 1981-09-11

Family

ID=11992647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1919880A Pending JPS56116156A (en) 1980-02-20 1980-02-20 Circuit check system for information processor

Country Status (1)

Country Link
JP (1) JPS56116156A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5250134A (en) * 1975-10-20 1977-04-21 Toshiba Corp Prom tester
JPS5333539A (en) * 1976-09-09 1978-03-29 Matsushita Electric Ind Co Ltd Memory test unit
JPS5426631A (en) * 1977-07-29 1979-02-28 Omron Tateisi Electronics Co Inspection system of rom

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5250134A (en) * 1975-10-20 1977-04-21 Toshiba Corp Prom tester
JPS5333539A (en) * 1976-09-09 1978-03-29 Matsushita Electric Ind Co Ltd Memory test unit
JPS5426631A (en) * 1977-07-29 1979-02-28 Omron Tateisi Electronics Co Inspection system of rom

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