JPS56140458A - Control system for priority order for common bus use - Google Patents

Control system for priority order for common bus use

Info

Publication number
JPS56140458A
JPS56140458A JP4197780A JP4197780A JPS56140458A JP S56140458 A JPS56140458 A JP S56140458A JP 4197780 A JP4197780 A JP 4197780A JP 4197780 A JP4197780 A JP 4197780A JP S56140458 A JPS56140458 A JP S56140458A
Authority
JP
Japan
Prior art keywords
lines
bus use
processors
combinations
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4197780A
Other languages
Japanese (ja)
Other versions
JPS6149712B2 (en
Inventor
Masahiro Yoshida
Hiroaki Nojiri
Keiichi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP4197780A priority Critical patent/JPS56140458A/en
Publication of JPS56140458A publication Critical patent/JPS56140458A/en
Publication of JPS6149712B2 publication Critical patent/JPS6149712B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Abstract

PURPOSE:To enable to control the bus use of many processors with a small number of bus signal lines, by weighting respective bus use request lines and by adding priority order to respective processors, in a multiprocessor system. CONSTITUTION:In a multiprocessor system where plural processors 1 and 2 are connected to the common bus in parallel, n-number bus use request lines BRQ1- BRQ5 for the common bus are provided, and combinations of r-number lines, in this example, 2 lines selected from n-number lines, in this example, 5 lines are assigned to respective processors, and respective bus use request lines given preliminarily to combinations are weighted, and priority levels 7 and 9 are added to respective processors 1 and 2 by combinations of r-number lines, in this example, 2 lines, and states of bus use request lines other than assigned those are monitored to make the common bus use of respective processors (1) and (2) possible according to priority order Consequently, the right of bus use of processors whose number is equal to the number of combinations nCr is controlled.
JP4197780A 1980-04-02 1980-04-02 Control system for priority order for common bus use Granted JPS56140458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4197780A JPS56140458A (en) 1980-04-02 1980-04-02 Control system for priority order for common bus use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4197780A JPS56140458A (en) 1980-04-02 1980-04-02 Control system for priority order for common bus use

Publications (2)

Publication Number Publication Date
JPS56140458A true JPS56140458A (en) 1981-11-02
JPS6149712B2 JPS6149712B2 (en) 1986-10-30

Family

ID=12623250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4197780A Granted JPS56140458A (en) 1980-04-02 1980-04-02 Control system for priority order for common bus use

Country Status (1)

Country Link
JP (1) JPS56140458A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979331A (en) * 1982-10-29 1984-05-08 Fuji Electric Co Ltd Controlling system for using bus
JPS60117362A (en) * 1983-11-30 1985-06-24 Fujitsu Ltd Bus controlling system
JPS6162159A (en) * 1984-08-23 1986-03-31 シーメンス、アクチエンゲゼルシヤフト Bidirectional data exchange

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50128955A (en) * 1974-03-29 1975-10-11
JPS52124829A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp Common buss control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50128955A (en) * 1974-03-29 1975-10-11
JPS52124829A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp Common buss control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979331A (en) * 1982-10-29 1984-05-08 Fuji Electric Co Ltd Controlling system for using bus
JPS60117362A (en) * 1983-11-30 1985-06-24 Fujitsu Ltd Bus controlling system
JPS6162159A (en) * 1984-08-23 1986-03-31 シーメンス、アクチエンゲゼルシヤフト Bidirectional data exchange

Also Published As

Publication number Publication date
JPS6149712B2 (en) 1986-10-30

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