JPS5481741A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5481741A
JPS5481741A JP14963077A JP14963077A JPS5481741A JP S5481741 A JPS5481741 A JP S5481741A JP 14963077 A JP14963077 A JP 14963077A JP 14963077 A JP14963077 A JP 14963077A JP S5481741 A JPS5481741 A JP S5481741A
Authority
JP
Japan
Prior art keywords
controller
data
processing
units
taken
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14963077A
Other languages
Japanese (ja)
Inventor
Noboru Murai
Kaoru Ikeda
Yukio Unosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14963077A priority Critical patent/JPS5481741A/en
Publication of JPS5481741A publication Critical patent/JPS5481741A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To enable to select the processing of each data processor to either of parallel and master slave processing mode, by giving the functions requesting the processing to the data processor, to the controller receiving the data inputted from the terminal unit.
CONSTITUTION: In the system providing the controller 2 receiving the data from a plurality of terminal units 3-0, 3-1 ... 3-n, and the data processors 1-0 and 1-1 executing the processing based on the data from the controller 2, the controller 2 is provided with the distribution circuit 4 parallely feeding the data to the units 1-0 and 1-1 and feeding either of them selectively, collation circuit 3 collating the result of processing, and the selection circuit 5 connecting the controller 2 to the units 1-0 and 1-1. Further, the selection control unit 9 is controlled with the controller 2, and the units 1-1 and 1-0 are taken as parallel processing mode or master slave processing mode in which one is taken as master and another is taken as slave processor.
COPYRIGHT: (C)1979,JPO&Japio
JP14963077A 1977-12-13 1977-12-13 Data processing system Pending JPS5481741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14963077A JPS5481741A (en) 1977-12-13 1977-12-13 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14963077A JPS5481741A (en) 1977-12-13 1977-12-13 Data processing system

Publications (1)

Publication Number Publication Date
JPS5481741A true JPS5481741A (en) 1979-06-29

Family

ID=15479417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14963077A Pending JPS5481741A (en) 1977-12-13 1977-12-13 Data processing system

Country Status (1)

Country Link
JP (1) JPS5481741A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822469A (en) * 1981-08-04 1983-02-09 Taisei Corp Central monitoring controller
JPH033060A (en) * 1989-05-31 1991-01-09 Nec Corp Automatic operation control system for two computer system
US6334194B1 (en) 1997-11-07 2001-12-25 Nec Corporation Fault tolerant computer employing double-redundant structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822469A (en) * 1981-08-04 1983-02-09 Taisei Corp Central monitoring controller
JPH033060A (en) * 1989-05-31 1991-01-09 Nec Corp Automatic operation control system for two computer system
US6334194B1 (en) 1997-11-07 2001-12-25 Nec Corporation Fault tolerant computer employing double-redundant structure

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