JPS56114343A - Chip structure for automatic wafer alignment - Google Patents
Chip structure for automatic wafer alignmentInfo
- Publication number
- JPS56114343A JPS56114343A JP1750380A JP1750380A JPS56114343A JP S56114343 A JPS56114343 A JP S56114343A JP 1750380 A JP1750380 A JP 1750380A JP 1750380 A JP1750380 A JP 1750380A JP S56114343 A JPS56114343 A JP S56114343A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- regions
- chip structure
- automatically
- wafer alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
PURPOSE:To align a wafer automatically by properly giving limited regions at the outside of a bonding pad row against individual chip structure in the wafer. CONSTITUTION:One chip in a wafer has an Al pad row 1 for test, and regions 2- 5 are semiconductor regions. Limiting conditions are given to the regions 2-5 for automatically aligning the wafer. The conditions are as follows. A specified mark is inserted, e.g. to one location of the regions 2-5 or the L-shaped regions of 2- 3 or either one of them, or the location is changed into a mirror surface or made to cause a diffused-reflection. The direction of the wafer is easily confirmed by the limitation, and the wafer is readily aligned automatically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1750380A JPS56114343A (en) | 1980-02-14 | 1980-02-14 | Chip structure for automatic wafer alignment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1750380A JPS56114343A (en) | 1980-02-14 | 1980-02-14 | Chip structure for automatic wafer alignment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56114343A true JPS56114343A (en) | 1981-09-08 |
Family
ID=11945781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1750380A Pending JPS56114343A (en) | 1980-02-14 | 1980-02-14 | Chip structure for automatic wafer alignment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56114343A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5536974A (en) * | 1992-05-22 | 1996-07-16 | Sumitomo Electric Industries, Ltd. | Semiconductor device with light reflecting substrate area |
-
1980
- 1980-02-14 JP JP1750380A patent/JPS56114343A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5536974A (en) * | 1992-05-22 | 1996-07-16 | Sumitomo Electric Industries, Ltd. | Semiconductor device with light reflecting substrate area |
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