JPS56111266A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56111266A
JPS56111266A JP1419780A JP1419780A JPS56111266A JP S56111266 A JPS56111266 A JP S56111266A JP 1419780 A JP1419780 A JP 1419780A JP 1419780 A JP1419780 A JP 1419780A JP S56111266 A JPS56111266 A JP S56111266A
Authority
JP
Japan
Prior art keywords
well layer
film
mask
level difference
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1419780A
Other languages
Japanese (ja)
Inventor
Katsuyuki Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1419780A priority Critical patent/JPS56111266A/en
Publication of JPS56111266A publication Critical patent/JPS56111266A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To reduce deterioration of characteristic such as junction leak by a method wherein the level difference of Si used for mask-matching after formation of a well layer can be formed in a heat treatment process after injection of ion into the well layer. CONSTITUTION:A thermo-oxidized film 2 is formed on an N type Si semiconductor substrate 1 and further thereon a nitrified film 9 is formed. Next, by using a photoresist 3 as a mask, the film 8 located in a region where the P well layer is formed is removed. Then, by using the resist 3 and the film 9 as the mask, a boron ion is injected, through the intermediary of the film 2, into the region where the P well layer is formed. Next, after the resist 3 being removed, oxidization for intrusion of the P well layer and for formation of the level difference of Si for mask-matching applied ina subsequent process is performed simultaneously by application of heat treatment in an inactive fas containing oxygen. By forming the level difference of Si in this way without application of thermal oxidization for hours, deterioration of characteristic such as junction leak harmful for C-MOSIC can be reduced.
JP1419780A 1980-02-07 1980-02-07 Manufacture of semiconductor device Pending JPS56111266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1419780A JPS56111266A (en) 1980-02-07 1980-02-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1419780A JPS56111266A (en) 1980-02-07 1980-02-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56111266A true JPS56111266A (en) 1981-09-02

Family

ID=11854387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1419780A Pending JPS56111266A (en) 1980-02-07 1980-02-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56111266A (en)

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