JPS56107557A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56107557A
JPS56107557A JP956180A JP956180A JPS56107557A JP S56107557 A JPS56107557 A JP S56107557A JP 956180 A JP956180 A JP 956180A JP 956180 A JP956180 A JP 956180A JP S56107557 A JPS56107557 A JP S56107557A
Authority
JP
Japan
Prior art keywords
domain
substrate
diffused
passivation layer
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP956180A
Other languages
Japanese (ja)
Inventor
Masamitsu Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP956180A priority Critical patent/JPS56107557A/en
Publication of JPS56107557A publication Critical patent/JPS56107557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a passivation layer easily by a method wherein a counter conductive domain is provided on a substrate having a selective diffused domain more shallowly than said domain, the diffused domain is anodized and converted into a porous insulator domain through insulating treatment, and the substrate is covered with an insulated film on the surface. CONSTITUTION:A low specific resistance of N<+> selective diffused domain 17 is formed on a high specific resistance of N<+> N<-> substrate 100 with a mesa type NPN transistor. Next, a P type base domain 3 is diffused more shallowly than said domain. The substrate is anodized in a 49% fluoric acid with platinum as a cathode to convert the N<+> domain 17 into a porous Si domain 18. Then, the substrate is heated in an oxidizing or nitrifying atmosphere to insulation, the domain 18 is converted into an insulator domain working as a passivation layer, and an insulated film 20 is formed on the substrate surface. An emitter domain 5 and electrodes 8, 9, 10 are provided with the insulated film as a mask, and an insulator domain 19 is cut at the center to obtain a mesa type transistor. The passivation layer can thus be formed easily.
JP956180A 1980-01-29 1980-01-29 Manufacture of semiconductor device Pending JPS56107557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP956180A JPS56107557A (en) 1980-01-29 1980-01-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP956180A JPS56107557A (en) 1980-01-29 1980-01-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56107557A true JPS56107557A (en) 1981-08-26

Family

ID=11723693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP956180A Pending JPS56107557A (en) 1980-01-29 1980-01-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56107557A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102985A (en) * 1972-04-07 1973-12-24
JPS5278384A (en) * 1975-12-25 1977-07-01 Nec Corp Production of semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102985A (en) * 1972-04-07 1973-12-24
JPS5278384A (en) * 1975-12-25 1977-07-01 Nec Corp Production of semiconductor integrated circuit device

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