JPS56107377A - Data processing system having partial purge tlb function - Google Patents

Data processing system having partial purge tlb function

Info

Publication number
JPS56107377A
JPS56107377A JP974380A JP974380A JPS56107377A JP S56107377 A JPS56107377 A JP S56107377A JP 974380 A JP974380 A JP 974380A JP 974380 A JP974380 A JP 974380A JP S56107377 A JPS56107377 A JP S56107377A
Authority
JP
Japan
Prior art keywords
register
entry
error
ineffective
tlb4a
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP974380A
Other languages
Japanese (ja)
Inventor
Kenichiro Miyazaki
Koichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP974380A priority Critical patent/JPS56107377A/en
Publication of JPS56107377A publication Critical patent/JPS56107377A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent execution of a partial purge in an erronous form, by making ineffective the designation entry on TLB when an error check circuit does not detect an error and making the entire entry on TLB when any error is detected. CONSTITUTION:The real page address is set to the register 10, and the access to TLB4A by the address counter 6 is started and the entry is sequentially read out one by one. One entry is read out on the register 9, the content of the real page address described and the register 10 are compared, and when in agreement, the entry is made ineffective to write in TLB4A. If any error is present on the real page address set to the register 10, the parity display flag V is changed to ineffective display to all the entries transcribed to the register 8. Further, the content of the register 10 is logged. Thus, the entry to be made ineffective is not left on TLB4A.
JP974380A 1980-01-30 1980-01-30 Data processing system having partial purge tlb function Pending JPS56107377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP974380A JPS56107377A (en) 1980-01-30 1980-01-30 Data processing system having partial purge tlb function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP974380A JPS56107377A (en) 1980-01-30 1980-01-30 Data processing system having partial purge tlb function

Publications (1)

Publication Number Publication Date
JPS56107377A true JPS56107377A (en) 1981-08-26

Family

ID=11728784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP974380A Pending JPS56107377A (en) 1980-01-30 1980-01-30 Data processing system having partial purge tlb function

Country Status (1)

Country Link
JP (1) JPS56107377A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428757A (en) * 1987-07-24 1989-01-31 Hitachi Ltd Address converting buffer control system
US4849881A (en) * 1983-10-26 1989-07-18 Kabushiki Kaisha Toshiba Data processing unit with a TLB purge function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849881A (en) * 1983-10-26 1989-07-18 Kabushiki Kaisha Toshiba Data processing unit with a TLB purge function
JPS6428757A (en) * 1987-07-24 1989-01-31 Hitachi Ltd Address converting buffer control system

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